HFA1109 查看數據表（PDF） - Intersil
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HFA1109 Datasheet PDF : 12 Pages
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HFA1109
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1109 design is
optimized for a 250Ω RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN (ACL)
RF (W)
BANDWIDTH (MHz)
-1
200
400
+1
250 (+RS = 550W) PDIP
350
250 (+RS = 700W) SOIC
+2
250
450
+5
100
160
+10
90
70
Table 1 lists recommended RF values, and the expected
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (+RS) in series with +IN is required to reduce gain
peaking and increase stability
PC Board Layout
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must! Attention should be given to
decoupling the power supplies. A large value (10μF)
tantalum in parallel with a small value (0.1μF) chip capacitor
works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to ground
seen by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Thus it is recommended that
the ground plane be removed under traces connected to -IN,
and connections to -IN should be kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth. By decreasing RS as CL increases, the
maximum bandwidth is obtained without sacrificing stability.
In spite of this, bandwidth still decreases as the load
capacitance increases.
Evaluation Board
The performance of the HFA1105 may be evaluated using
the HFA11XX Evaluation Board and a SOIC to DIP adaptor
like the Aries Electronics Part Number 14-350000-10. The
layout and schematic of the board are shown in Figure 1.
Please contact your local sales office for information. When
evaluating this amplifier, the two 510Ω gain setting resistors
on the evaluation board should be changed to 250Ω..
510Ω
510Ω
VH
1
50Ω
2
IN
3
10µF
4
0.1µF
-5V
8
7
6
5
GND
0.1µF
10µF
50Ω
+5V
OUT
VL
GND
FIGURE 1A. BOARD SCHEMATIC
VH
1
+IN
OUT V+
VL V-
GND
FIGURE 1B. TOP LAYOUT
FIGURE 1C. BOTTOM LAYOUT
FIGURE 1. EVALUATION BOARD SCHEMATICS AND LAYOUT
5
FN4019.5
April 23, 2007
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