IDT723611 查看數據表（PDF） - Integrated Device Technology

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IDT723611

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

COMMERCIAL TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

mailbox register has a flag to signal when new mail has been

stored. Parity is checked passively on each port and may be

ignored if not desired. Parity generation can be selected for

data read from each port. Two or more devices may be used

in parallel to create wider data paths.

The IDT723611 is a synchronous (clocked) FIFO, mean-

ing each port employs a synchronous interface. All data

transfers through a port are gated to the LOW-to-HIGH

transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asyn-

chronous or coincident. The enables for each port are ar-

ranged to provide a simple bidirectional interface between

microprocessors and/or buses with synchronous control.

The Full-Flag (FF) and Almost-Full (AF) flag of the FIFO are

two-stage synchronized to the port clock that writes data into

its array (CLKA). The Empty Flag (EF) and Almost-Empty (AE)

flag of the FIFO are two-stage synchronized to the port clock

that reads data from its array.

The IDT723611 is characterized for operation from 0°C to

70°C.

PIN CONFIGURATION

A23 1

A22 2

A21 3

GND 4

A20 5

A19 6

A18 7

A17 8

A16 9

A15 10

A14 11

A13 12

A12 13

A11 14

A10 15

GND 16

A9 17

A8 18

A7 19

VCC 20

A6 21

A5 22

A4 23

A3 24

GND 25

A2 26

A1 27

A0 28

NC 29

NC 30

90 B22

89 B21

88 GND

87 B20

86 B19

85 B18

84 B17

83 B16

82 B15

81 B14

80 B13

79 B12

78 B11

77 B10

76 GND

75 B9

74 B8

73 B7

72 VCC

71 B6

70 B5

69 B4

68 B3

67 GND

66 B2

65 B1

64

63

B0

EF

62 AE

61 NC

Note:

1. NC = No internal connection

TQFP (PN120-1, order code: PF)

TOP VIEW

3024 drw 02

2

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