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IDT723611

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

Name

A0-A35 Port-A Data

AE

Almost-Empty Flag

AF

Almost-Full Flag.

B0-B35 Port-B Data.

CLKA Port-A Clock

CLKB Port-B Clock

CSA Port-A Chip Select

CSB Port-B Chip Select

EF

Empty Flag

ENA

ENB

FF

Port-A Enable

Port-B Enable

Full Flag

FS1, FS0 Flag-Offset Selects

MBA

MBB

Port-A Mailbox Select

Port-B Mailbox Select

MBF1 Mail1 Register Flag

I/O

Description

I/O 36-bit bidirectional data port for side A.

O Programmable almost-empty flag synchronized to CLKB. It is LOW when

the number of words in the FIFO is less than or equal to the value in the offset

register, X.

O Programmable almost-full flag synchronized to CLKA. It is LOW when the

number of empty locations in the FIFO is less than or equal to the value in the

offset register, X.

I/O 36-bit bidirectional data port for side B.

I CLKA is a continuous clock that synchronizes all data transfers through port-A

and can be aynchronous or coincident to CLKB. FF and AF are synchronized

to the LOW-to-HIGH transition of CLKA.

I CLKB is a continuous clock that synchronizes all data transfers through port-B

and can be asynchronous or coincident to CLKA. EF and AE are synchronized

to the LOW-to-HIGH transition of CLKB.

I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A. The A0-A35 outputs are in the high-impedance state

when CSA is HIGH.

I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B. The B0-B35 outputs are in the high-impedance state

when CSB is HIGH.

O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW,

the FIFO is empty, and reads from its memory are disabled. Data can be read

from the FIFO to its output register when EF is HIGH. EF is forced LOW when

the device is reset and is set HIGH by the second LOW-to-HIGH transition of

CLKB after data is loaded into empty FIFO memory.

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A.

I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B.

O FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW,

the FIFO is full, and writes to its memory are disabled. FF is forced LOW when

the device is reset and is set HIGH by the second LOW-to-HIGH transition of

CLKA after reset.

I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1,

which loads one of four preset values into the almost-full and almost-empty

offset register (X).

I A HIGH level on MBA chooses a mailbox register for a port-A read or write

operation.

I A HIGH level on MBB chooses a mailbox register for a port-B read or write

operation. When the B0-B35 outputs are active, a HIGH level on MBB selects

data from the mail1 register for output, and a LOW level selects the FIFO

output register data for output.

O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to

the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set

LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B

read is selected and MBB is HIGH. MBF1 is set HIGH when the device is

reset.

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