IDT72V845 查看數據表（PDF） - Integrated Device Technology

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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

RS

REN, WEN, LD

FL, RXI, WXI(1)

tRS

t RSR

tRSS

t RSR

CONFIGURATION SETTING

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK, WCLK (2)

FF/IR

t RSF

EF/OR

PAF, WXO/

HF, RXO

PAE

t RSF

t RSF

t RSF

FWFT Mode

IDT Standard Mode

Q0 - Q17

t RSF

OE = 1(3)

OE = 0

NOTES:

1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).

2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.

3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

4295 drw 05

Figure 5. Reset Timing(2)

WCLK

D0 - D17

WEN

FF

RCLK

t CLK

t CLKH

t CLKL

t DS

DATA IN VALID

tENS

tWFF

tSKEW1 (1)

t DH

tENH

t WFF

NO OPERATION

REN

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NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.

Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)

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