IDT72V845 查看數據表（PDF） - Integrated Device Technology

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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

WEN

tCLKH

tCLKL

(1)

tENS

tENH

PAF

RCLK

D - (m + 1) words in FIFO

tPAFA

D - m words

in FIFO

tPAFA

D - (m + 1) words

in FIFO

tENS

REN

4295 drw 14

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth.

In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:

D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.

3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.

4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.

Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

WCLK

WEN

HF

RCLK

REN

tCLKH

tCLKL

tENS

D/2 words in FIFO(2),

[ ] D-1

2

+1

words in FIFO(3)

tENH

tHF

D/2 + 1 words in FIFO(2),

[ ] D-1

2 +2

words in FIFO(3)

tHF

tENS

D/2 words in FIFO(2),

[ ] D-1

2 +1

words in FIFO(3)

4295 drw 15

NOTES:

1. D = maximum FIFO Depth.

In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:

D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.

Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)

16

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