IDT54FCT245AD 查看數據表（PDF） - Integrated Device Technology

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IDT54FCT245AD

3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

Integrated Device Technology 

IDT54/74FCT3245/A

3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol

∆ICC

Parameter

Test Conditions(1)

Quiescent Power Supply Current VCC = Max.

VIN = VCC – 0.6V(3)

Min. Typ.(2) Max. Unit

— 2.0 30 µA

ICCD

IC

Dynamic Power Supply

Current(4)

Total Power Supply Current(6)

VCC = Max.

Outputs Open

OE = DIR = GND

One Input Toggling

50% Duty Cycle

VCC = Max.

VIN = VCC

VIN = GND

VIN = VCC

—

60

85 µA/

MHz

— 0.6 0.9 mA

Outputs Open

VIN = GND

fi =10MHz

50% Duty Cycle

OE = DIR = GND

One Bit Toggling

VCC = Max.

Outputs Open

fi = 2.5MHz

50% Duty Cycle

OE = DIR = GND

Eight Bits Toggling

VIN = VCC –0.6V

VIN = GND

VIN = VCC

VIN = GND

VIN = VCC –0.6V

VIN = GND

— 0.6 0.9

—

1.2 1.7(5)

—

1.2 1.8(5)

NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 3.3V, +25°C ambient.

3. Per TTL driven input; all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

NCP = Number of Clock Inputs at fCP

fi = Input Frequency

Ni = Number of Inputs at fi

2650 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3)

FCT3245

FCT3245A

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH Propagation Delay

tPHL A to B, B to A

CL = 50pF

RL = 500Ω

1.5

7.0

1.5

7.5

1.5

4.6

1.5

4.9 ns

tPZH Output Enable Time

tPZL OE to A or B

1.5

9.5

1.5 10.0 1.5

6.2

1.5

6.5 ns

tPHZ Output Disable Time

tPLZ OE to A or B

1.5

7.5

1.5 10.0 1.5

5.0

1.5

6.0 ns

tPZH Output Enable Time

tPZL DIR to A or B(4)

1.5

9.5

1.5 10.0 1.5

6.2

1.5

6.5 ns

tPHZ Output Disable Time

1.5

7.5

1.5 10.0 1.5

5.0

1.5

6.0 ns

tPLZ DIR to A or B(4)

NOTES:

2650 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays

and Enable/Disable times should be degraded by 20%.

4. This parameter is guaranteed but not tested.

8.12

4

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