IDT79RV3081-40 查看數據表（PDF） - Integrated Device Technology

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IDT79RV3081-40

RISController with FPA

Integrated Device Technology 

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (Continued):

PIN NAME

I/O

DESCRIPTION

ALE

I/O Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus

transaction. This signal is used by external logic to capture the address for the transfer, typically using

transparent latches.

Rd

Wr

DataEn

Burst/

WrNear

Ack

During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to capture the write

target address for potential data cache invalidates.

O Read: An output which indicates that the current bus transaction is a read.

I/O Write: An output which indicates that the current bus transaction is a write. During coherent DMA, this input

indicates that the current transfer is a write.

O External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor during

read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus

without having a bus conflict occur. During write cycles, or when no bus transaction is occurring, this signal is

negated, thus disabling the external memory drivers

O Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read is

requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to

cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles if quad word refill

is currently selected.

On write transactions, the WrNear output tells the external memory system that the bus interface unit is

performing back-to-back write transactions to an address within the same 512 word page as the prior write

transaction. This signal is useful in memory systems which employ page mode or static column DRAMs, and

allows near writes to be retired quickly.

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently processed the

bus transaction, and that the CPU may either terminate the write cycle or process the read data from this read

transfer.

RdCEn

SysClk

BusReq

BusGnt

IvdReq

CohReq

During Coherent DMA, this input indicates that the current write transfer is completed, and that the internal

invalidation address counter should be incremented.

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed valid

data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer.

O System Reference Clock: An output from the CPU which reflects the timing of the internal processor "Sys"

clock. This clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus

interface unit. This clock will either be at the same frequency as the CPU execution rate clock, or at one-half

that frequency, as selected during reset.

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals

so that they may be driven by an external master.

O DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been detected, and

that the bus is relinquished to the external master.

I

Invalidate Request. An input provided by an external DMA controller to request that the CPU invalidate the

Data Cache line corresponding to the current DMA write target address. This signal is the same pin as Diag(0)

I

Coherent DMA Request. An input used by the external DMA controller to indicate that the requested DMA

operations could involve hardware cache coherency. This signal is the Rsvd(0) of the R3051.

SBrCond(3:2) I

BrCond(0)

BusError

I

Branch Condition Port: These external signals are internally connected to the CPU signals CpCond(3:0).

These signals can be used by the branch on co-processor condition instructions as input ports. There are two

types of Branch Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs, and

thus may be driven by asynchronous agents. The direct Branch Condition inputs must be driven synchronously.

Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal

is only sampled during read and write operations. If the bus transaction is a read operation, then the CPU will

take a bus error exception.

2889 tbl 03

5.5

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