IDT82V2058 查看數據表（PDF） - Integrated Device Technology

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IDT82V2058

OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Name

TD0/TDP0

TD1/TDP1

TD2/TDP2

TD3/TDP3

TD4/TDP4

TD5/TDP5

TD6/TDP6

TD7/TDP7

BPVI0/TDN0

BPVI1/TDN1

BPVI2/TDN2

BPVI3/TDN3

BPVI4/TDN4

BPVI5/TDN5

BPVI6/TDN6

BPVI7/TDN7

Type

I

Pin No.

QFP144 BGA160

Description

37

N2 TDn: Transmit Data for Channel 0~7

30

L2 When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data

80

L13 on TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3 line

73

N13 code rules before being transmitted to the line.

108

B13

101

D13 BPVIn: Bipolar Violation Insertion for Channel 0~7

8

D2 Bipolar violation insertion is available in Signal Rail mode 2 (see table-1) with AMI enabled. A low-

1

B2 to-high transition on this pin will make the next logic one to be transmitted on TDn pin the same

polarity as the previous pulse, and violate the AMI rule. This is for testing.

38

N3

31

L3 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7

79

L12 When the device is in Dual Rail mode, the NRZ data to be transmitted for positive/negative pulse

72

N12 is input on this pin. Data on TDPn/TDNn are active high and sampled into the device on falling

109

B12 edges of TCLKn. The line code in Dual Rail mode is as the follows :

102

D12

TDPn TDNn Output Pulse

7

D3

144

B3

0

0

Space

0

1

Negative Pulse

1

0

Positive Pulse

1

1

Space

TCLK0

TCLK1

TCLK2

TCLK3

TCLK4

TCLK5

TCLK6

TCLK7

Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the

corresponding channel into Single Rail mode 1 (see table-1 on Page13).

I

36

N1 TCLKn: Transmit Clock for Channel 0~7

29

L1 The clock of 2.048 MHz to be transmitted is input on this pin. The transmit data at TDn/TDPn or

81

L14 TDNn is sampled into the device on falling edges of TCLKn.

74

N14 Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in

107

B14 Transmit All One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts

100

D14 MCLK as the time reference.

9

D1 If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver

2

B1 output ports become high impedance.

The different operating modes of TCLKn are summarized as follows:

MCLK

TCLKn

Transmitter Mode

Clocked

Clocked

Normal operation

Clocked High (≥ 16 MCLK) Transmit All One (TAO) signals to line side in the

corresponding transmit channel.

Clocked Low (≥ 64 MCLK) Corresponding transmit channel is set into power down state.

High/Low TCLK1 is clocked TCLKn is clocked Normal operation

TCLKn is high Transmit All One (TAO) signals to the line

(≥ 16 TCLK1) side in the corresponding transmit channel.

TCLKn is low Corresponding transmit channel is set into

(≥ 64 TCLK1) power down state.

The receive path is not affected by the status of TCLK1.

When MCLK is high, all receive paths just slice the incoming

data stream. When MCLK is low, all the receive paths are

powered down.

High/Low TCLK1 is not All eight transmitters (TTIPn & TRINGn) will be in high

available impedance state.

(High/Low)

5

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