IDT82V2058 查看數據表（PDF） - Integrated Device Technology

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IDT82V2058

OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Name

MODE2

MODE1

MODE0

/CODE

Type

Pin No.

QFP144 BGA160

Description

Hardware/Host Control Mode

I

11

E2 MODE2: Control Mode Select 2

The signal on this pin determines which control mode is selected to control the device:

(Pulled

to

VDDIO

/2)

MODE2

Low

VDDIO/2

High

Control Interface

Control by Hardware mode

Control by Serial Host Interface

Control by Parallel Host Interface

Hardware control pins include MODE[2:0], TS[2:0], LOOP[7:0], CODE, CLKE, JAS and OE.

Serial host Interface pins include CS, SCLK, SDI, SDO and INT.

Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The

device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions

below for details):

MODE[2:0]

Host Interface

100

Non-multiplexed Motorola mode interface.

101

Non-multiplexed Intel mode interface.

110

Multiplexed Motorola mode interface.

111

Multiplexed Intel mode interface.

I

43

K2 MODE1: Control Mode Select 1

In parallel host mode, the parallel interface operates with separate address bus and data bus when this

pin is Low, and operates with multiplexed address and data bus when this pin is High.

In serial host mode and hardware mode, this pin should be grounded.

I

88 H12 MODE0: Control Mode Select 0

In host mode, the parallel host interface is configured for Motorola compatible hosts when this pin is Low,

or for Intel compatible hosts when this pin is High.

CODE: Line Code Rule Select

In hardware control mode, the HDB3 encoder/decoder is enabled when this pin is Low, and AMI

encoder/decoder is enabled when this pin is High. The selections affect all the channels.

CS/JAS I

87

(Pulled

to

VDDIO

/2)

In serial host mode, this pin should be grounded.

J11 CS: Chip Select (Active Low)

In host mode, this pin is asserted low by the host to enable host interface. A transition from High to Low

must occur on this pin for each Read/Write operation and the level must not return to High until the

operation is over.

JAS: Jitter Attenuator Select

In hardware control mode, this pin globally determines the Jitter Attenuator position:

JAS

Jitter Attenuator (JA) Configuration

Low

JA in transmit path

VDDIO/2

JA not used

High

JA in receive path

7

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