IDT82V2084 查看數據表（PDF） - Integrated Device Technology

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IDT82V2084

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

Table-1 Pin Description (Continued)

Name

THZ

REF

SCLKE

Type

Input

Input

Input

TQFP128

Description

4 THZ: Transmit Driver Enable

This pin enables or disables all transmitter drivers on a global basis. A low level on this pin enables the drivers while a high level

turns all drivers into high impedance state. Note that functionality of internal circuits is not affected by signal on this pin.

43 REF: Reference Resistor

An external resistor (3 KΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.

5 SCLKE: Serial Clock Edge Select

Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected as shown below:

TRST

TMS

TCK

TDO

TDI

VDDIO

GNDIO

VDDT1

VDDT2

VDDT3

VDDT4

GNDT1

GNDT2

GNDT3

GNDT4

VDDA

GNDA

VDDD

GNDD

VDDR1

VDDR2

VDDR3

VDDR4

SCLKE

Low

High

SCLK

Rising edge is active edge

Falling edge is active edge

Input

Pullup

JTAG Signals

123 TRST: JTAG Test Port Reset

This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic

operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.

For normal signal processing, this pin should be connected to ground.

Input

Pullup

124 TMS: JTAG Test Mode Select

This pin is used to control the test logic state machine and is sampled on the rising edges of TCK. TMS has an internal pull-up

resistor.

Input

127 TCK: JTAG Test Clock

This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising edges of TCK while the

data on TDO is clocked out of the device on the falling edges of TCK. When TCK is idle at a low level, all stored-state devices

contained in the test logic will retain their state indefinitely.

Output

Tri-state

126 TDO: JTAG Test Data Output

This is a tri-state output signal and used for reading all the serial configuration and test data from the test logic. The data on TDO

is clocked out of the device on the falling edges of TCK.

Input

Pullup

125 TDI: JTAG Test Data Input

This pin is used for loading instructions and data into the test logic and has an internal pullup resistor. The data on TDI is clocked

into the device on the rising edges of TCK.

Power Supplies and Grounds

-

13, 22 3.3V I/O Power Supply

68, 81

99

-

12, 23 I/O Ground

69, 83

98

- 101, 102 3.3V Power Supply for Transmitter Driver

111, 112

45, 46

55, 56

- 105, 106 Analog Ground for Transmitter Driver

115, 116

49, 50

59, 60

- 44, 121 3.3V Analog Core Power Supply

- 41, 122 Core Analog Ground

-

9, 85 3.3V Digital Core Power Supply

-

11, 84 Core Digital Ground

-

110 3.3V Power Supply for Receiver

120

54

64

12

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