IDT82V2084 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

比赛名单

IDT82V2084

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3 FUNCTIONAL DESCRIPTION

3.1 T1/E1/J1 MODE SELECTION

The IDT82V2084 can be used as a four-channel E1 LIU or a four-chan-

nel T1/J1 LIU. In E1 application, the T1E1 bit (GCF0, 40H) should be set

to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.

3.2 TRANSMIT PATH

The transmit path of each channel of the IDT82V2084 consists of an

Encoder, an optional Jitter Attenuator, a Waveform Shaper, a set of LBOs,

a Line Driver and a Programmable Transmit Termination.

3.2.1 TRANSMIT PATH SYSTEM INTERFACE

The transmit path system interface consists of TCLKn pin, TDn/TDPn

pin and TDNn pin. In E1 mode, the TCLKn is a 2.048 MHz clock. In T1/J1

mode, the TCLKn is a 1.544 MHz clock. If the TCLKn is missing for more

than 70 MCLK cycles, an interrupt will be generated if it is not masked.

Transmit data is sampled on the TDn/TDPn and TDNn pins by the active

edge of TCLKn. The active edge of TCLKn can be selected by the

TCLK_SEL bit (TCF0, 02H...). And the active level of the data on TDn/TDPn

and TDNn can be selected by the TD_INV bit (TCF0, 02H...).

The transmit data from the system side can be provided in two different

ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used

for transmitting data and the T_MD[1] bit (TCF0, 02H...) should be set to

‘0’. In Dual Rail Mode, both TDPn and TDNn pins are used for transmitting

data, the T_MD[1] bit (TCF0, 02H...) should be set to ‘1’.

3.2.2 ENCODER

When T1/J1 mode is selected, in Single Rail mode, the Encoder can be

selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit

(TCF0, 02H...).

When E1 mode is selected, in Single Rail mode, the Encoder can be con-

figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit

(TCF0, 02H...).

In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit

T_MD[1] is ‘1’), the Encoder is by-passed. In the Dual Rail mode, a logic ‘1’

on the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse

on the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin

results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn

are logic ‘1’ or logic ‘0’, the TTIPn/TRINGn outputs a space (Refer to TDn/

TDPn, TDNn Pin Description).

3.2.3 PULSE SHAPER

The IDT82V2084 provides three ways of manipulating the pulse shape

before sending it. The first is to use preset pulse templates for short haul

application, the second is to use LBO (Line Build Out) for long haul appli-

cation and the other way is to use user-programmable arbitrary waveform

template.

3.2.3.1 Preset Pulse Templates

For E1 applications, the pulse shape is shown in Figure-3 according to

the G.703 and the measuring diagram is shown in Figure-4. In internal

impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]

bits (TCF1, 03H...) should be set to ‘0000’; if the cable impedance is 120

Ω, the PULS[3:0] bits (TCF1, 03H...) should be set to ‘0001’. In external

impedance matching mode, for both E1/75 Ω and E1/120 Ω cable imped-

ance, PULS[3:0] should be set to ‘0001’.

1 .2 0

1 .0 0

0 .8 0

0 .6 0

0 .4 0

0 .2 0

0 .0 0

-0 .2 0

-0 .6

-0.4

-0.2

0

0 .2

0.4

0 .6

Tim e in U nit Intervals

Figure-3 E1 Waveform Template Diagram

TTIPn

IDT82V2084

TRINGn

RLOAD

VOUT

Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom)

2. For RLOAD =120 Ω (nom), Vout (Peak)=3.00V (nom)

Figure-4 E1 Pulse Template Test Circuit

For T1 applications, the pulse shape is shown in Figure-5 according to

the T1.102 and the measuring diagram is shown in Figure-6. This also

meets the requirement of G.703, 2001. The cable length is divided into five

grades, and there are five pulse templates used for each of the cable length.

The pulse template is selected by PULS[3:0] bits (TCF1, 03H...).

1.2

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

0

250

500

750

1000

1250

Time (ns)

Figure-5 DSX-1 Waveform Template

14

Share Link: