IDT82V2084 查看數據表（PDF） - Integrated Device Technology

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IDT82V2084

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

2 PIN DESCRIPTION

Table-1 Pin Description

Name

TTIP1

TTIP2

TTIP3

TTIP4

Type TQFP128

Description

Transmit and Receive Line Interface

Output

Analog

104 TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~4

114 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high on

48 THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/TRINGn in the cor-

58 responding channel is set to high impedance state.

TRING1

TRING2

TRING3

TRING4

RTIP1

RTIP2

RTIP3

RTIP4

Input

Analog

103 In summary, these pins will become high impedance in the following conditions:

113

47

•

•

THZ pin is high: all TTIPn/TRINGn enter high impedance.

THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;

57 • Loss of MCLK: all TTIPn/TRINGn pins become high impedance;

• Loss of TCLKn: the corresponding TTIPn/TRINGn become high impedance (exceptions: Remote Loopback; Transmit

internal pattern by MCLK);

• Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;

• After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.

109 RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~4

119 These pins are the differential line receiver inputs.

53

63

RRING1

RRING2

RRING3

RRING4

TD1/TDP1

TD2/TDP2

TD3/TDP3

TD4/TDP4

Input

108

118

52

62

Transmit and Receive Digital Data Interface

96 TDn: Transmit Data for Channel 1~4

90 In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled into the device on the active

80 edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...). Data is encoded by AMI, HDB3 or

74 B8ZS line code rules before being transmitted to the line. In this mode, TDNn should be connected to ground.

TDN1

TDN2

TDN3

TDN4

TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~4

95 In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sampled into the device on

89 the active edge of TCLKn. The active edge of the TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...) The line code in Dual

79 Rail Mode is as follows:

73

TDPn

TDNn

Output Pulse

0

0 Space

0

1 Positive Pulse

1

0 Negative Pulse

1

1 Space

TCLK1

TCLK2

TCLK3

TCLK4

Input

97 TCLKn: Transmit Clock for Channel 1~4

91 These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data on TDn/TDPn or TDNn

82 is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is not masked,

75 an interrupt will be generated.

Notes:

1. The footprint ‘n’ (n = 1~4) represents one of the four channels.

2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by '...'. Users can find

these omitted addresses in the Register Description section.

3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles.

9

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