IS61C1024 查看數據表（PDF） - Integrated Silicon Solution
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IS61C1024 Datasheet PDF : 10 Pages
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IS61C1024
IS61C1024L
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
Symbol Parameter
tWC Write Cycle Time
tSCE1 CE1 to Write End
tSCE2 CE2 to Write End
tAW Address Setup Time to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWE(4) WE Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE(5) WE LOW to High-Z Output
tLZWE(5) WE HIGH to Low-Z Output
-12 ns(3)
Min. Max.
12 —
10 —
10 —
10 —
0—
0—
10 —
7—
0—
—7
2—
-15 ns
Min. Max.
15 —
12 —
12 —
12 —
0—
0—
10 —
8—
0—
—7
2—
-20 ns
Min. Max.
20 —
15 —
15 —
15 —
0—
0—
12 —
10 —
0—
— 10
2—
-25 ns
Min. Max. Unit
25 —
ns
20 —
ns
20 —
ns
20 —
ns
0—
ns
0—
ns
15 —
ns
12 —
ns
0—
ns
— 12
ns
2—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IS61C1024 only.
4. Tested with OE HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
7
SR028-1K
05/12/99
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