ISL8022 查看數據表（PDF） - Intersil
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ISL8022 Datasheet PDF : 18 Pages
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ISL8022
Ordering Information
Pin Configuration
PART NUMBER PART
(Notes 1, 2, 3) MARKING
TEMP.
RANGE
(°C)
PKG.
PACKAGE DWG.
(Pb-Free) #
ISL8022IRZ
8022
-40 to +85 12 Ld 4x3 L12.4x3
DFN
ISL8022EVAL1Z Evaluation Board
NOTES:
1. Add “T” suffix for Tape and Reel. Please refer to TB347 for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL8022. For more information on MSL
please see techbrief TB363.
ISL8022
(12 LD DFN)
TOP VIEW
FB1 1
EN1 2
PG 3
VIN1 4
LX1 5
PGND1 6
PAD
12 FB2
11 EN2
10 SYNC
9 VIN2
8 LX2
7 PGND2
Pin Description
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
-
SYMBOL
DESCRIPTION
FB1 The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance
error amplifier. The output voltage is set by an external resistor divider connected to FB1. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to
monitor the Channel 1 regulator output voltage.
EN1
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1
and discharge output capacitor when driven to low. Do not leave this pin floating.
PG
VIN1
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the
VOUT1 and VOUT2 voltages. There is an internal 1MΩ pull-up resistor.
Input supply voltage for Channel 1. Connect 10µF ceramic capacitor to PGND1.
LX1 Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.
PGND1 Negative supply for power stage 1.
PGND2 Negative supply for power stage 2 and system ground.
LX2
VIN2
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Input supply voltage for Ch 2 and to provide logic bias. Make sure that VIN2 is ≥ VIN1. Connect 10µF
ceramic capacitor to PGND2.
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or
ground for forced PWM mode. Connect to an external function generator for Synchronization. Negative
edge trigger. Do not leave this pin floating.
EN2
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2
and discharge output capacitor when driven to low. Do not leave this pin floating.
FB2 The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance
error amplifier. The output voltage is set by an external resistor divider connected to FB2. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to
monitor the Channel 2 regulator output voltage.
EXPOSED The exposed pad must be connected to the SGND pin for proper electrical performance. Add as much
PAD vias as possible for optimal thermal performance.
4
FN7650.1
August 25, 2010
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