ISL8487 查看數據表（PDF） - Intersil
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ISL8487 Datasheet PDF : 13 Pages
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ISL8487, ISL81483, ISL81487
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C,
(Note 2) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C) MIN
TYP MAX UNITS
Receiver Input Resistance
RIN
-7V ≤ VCM ≤ 12V
ISL81483, ISL81487 Full
96
-
ISL8487
Full
48
-
-
kΩ
-
kΩ
No-Load Supply Current, (Note 3)
ICC
ISL81487, DI, RE = 0V DE = VCC
or VCC
DE = 0V
Full
-
400 500 μA
Full
-
350 420 μA
ISL8487, ISL81483, DI, DE = VCC
RE = 0V or VCC
DE = 0V
Full
-
160 200 μA
Full
-
120 145 μA
Shutdown Supply Current
ISHDN (Note 7), DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
0.5
8
μA
Driver Short-Circuit Current,
VO = High or Low
IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V, (Note 4)
Full
35
-
250 mA
Receiver Short-Circuit Current
IOSR 0V ≤ VO ≤ VCC
Full
7
-
85
mA
SWITCHING CHARACTERISTICS (ISL81487)
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Output Skew
tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3)
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3)
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Receiver Skew | tPLH - tPHL |
tSKD (Figure 4)
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5)
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Maximum Data Rate
fMAX
SWITCHING CHARACTERISTICS (ISL8487, ISL81483)
Full
15
24
50
ns
Full
-
2
10
ns
Full
3
12
25
ns
Full
-
14
70
ns
Full
-
14
70
ns
Full
-
44
70
ns
Full
-
21
70
ns
Full
30
90
150
ns
25
-
5
-
ns
Full
-
9
50
ns
Full
-
9
50
ns
Full
-
9
50
ns
Full
-
9
50
ns
Full
5
-
-
Mbps
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Output Skew
tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3, Note 5)
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3, Note 5)
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Receiver Skew | tPLH - tPHL |
tSKD (Figure 4)
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5, Note 6)
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5, Note 6)
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Maximum Data Rate
fMAX
Time to Shutdown
tSHDN (Note 7)
Full 250 650 2000 ns
Full
-
160
800
ns
Full 250 900 2000 ns
Full 250 1000 2000 ns
Full 250 860 2000 ns
Full 300 660 3000 ns
Full 300 640 3000 ns
Full 250 500 2000 ns
25
-
60
-
ns
Full
-
10
50
ns
Full
-
10
50
ns
Full
-
10
50
ns
Full
-
10
50
ns
Full 250
-
-
kbps
Full
50
120
600
ns
5
FN6050.7
July 31, 2006
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