K6R1004C1D(2004) 查看數據表（PDF） - Samsung
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K6R1004C1D Datasheet PDF : 9 Pages
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K6R1004C1D
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
K6R1004C1D-10
Min
10
7
0
7
7
10
0
0
5
0
3
* The above parameters are also guaranteed at industrial temperature range.
Max
-
-
-
-
-
-
-
5
-
-
-
PRELIMINARY
PRELIMINARY
CMOS SRAM
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tRC
tOH
tAA
Previous Valid Data
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
tRC
tAA
tCO
OE
Data out
VCC
Current
High-Z
ICC
ISB
tOE
tOLZ
tLZ(4,5)
tPU
50%
tHZ(3,4,5)
Valid Data
tOHZ
tDH
tPD
50%
-6-
Rev. 3.0
July 2004
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