LIS3DH 查看數據表（PDF） - STMicroelectronics
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LIS3DH
STMicroelectronics
LIS3DH Datasheet PDF : 42 Pages
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Mechanical and electrical specifications
LIS3DH
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values
Symbol
Parameter
tc(SPC)
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
tv(SO)
th(SO)
tdis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
Value (1)
Min
Max
100
10
6
8
5
15
50
9
50
Unit
ns
MHz
ns
Figure 3. SPI slave timing diagram
CS (3)
SPC (3)
tsu(CS)
SDI (3)
SDO (3)
tc(SPC)
tsu(SI)
th(SI)
MSB IN
tv(SO)
MSB OUT
th(SO)
(3)
th(CS)
(3)
LSB IN
(3)
tdis(SO)
LSB OUT
(3)
Note: 1 Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production.
2 Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.
3 When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal
pull-up resistors.
12/42
Doc ID 17530 Rev 1
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