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LIS3DH 查看數據表(PDF) - STMicroelectronics

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LIS3DH Datasheet PDF : 42 Pages
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Digital interfaces
6
Digital interfaces
LIS3DH
The registers embedded inside the LIS3DH may be accessed through both the I2C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS
line must be tied high (i.e. connected to Vdd_IO).
Table 10. Serial interface pin description
Pin name
Pin description
CS
SCL
SPC
SDA
SDI
SDO
SA0
SDO
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
I2C serial clock (SCL)
SPI serial port clock (SPC)
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I2C less significant bit of the device address (SA0)
SPI serial data output (SDO)
6.1
I2C serial interface
The LIS3DH I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 11. Serial interface pin description
Term
Description
Transmitter
Receiver
Master
Slave
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
transfer
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
20/42
Doc ID 17530 Rev 1

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