LIS3DSH 查看數據表（PDF） - STMicroelectronics
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LIS3DSH
STMicroelectronics
LIS3DSH Datasheet PDF : 53 Pages
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Mechanical and electrical specifications
LIS3DSH
3.3
3.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values
Symbol
Parameter
Value (1)
Min.
Max.
Unit
tc(SPC)
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
tv(SO)
th(SO)
tdis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
ns
10
MHz
6
8
5
15
ns
50
9
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 3. SPI slave timing diagram (c)
CS (2)
SPC (2)
tsu(CS)
tsu(SI)
th(SI)
tc(SPC)
(2)
th(CS)
(2)
SDI (2)
M SB IN
tv(SO)
th(SO )
LSB IN
(2)
tdis(SO )
SDO (2)
M SB OUT
LSB O UT
(2)
2. When no communication is on-going, data on SDO is driven by internal pull-up resistor.
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c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
Doc ID 022405 Rev 1
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