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LIS3DSH 查看數據表(PDF) - STMicroelectronics

零件编号
产品描述 (功能)
比赛名单
LIS3DSH Datasheet PDF : 53 Pages
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LIS3DSH
4
Application hints
Figure 5. LIS3DSH electrical connection
Vdd
Application hints
10µF
100nF
Vdd_IO
16
1
14
13
NC
NC
TOP VIEW
INT1/DRDY
5
6
9
8
INT 2
GND
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
AM10211V1
The device core is supplied through the Vdd line while the I/O pins are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF) should be placed
as near as possible to pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2C or SPI interfaces. When using the I2C, CS must be tied high.
4.1
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com.
Doc ID 022405 Rev 1
19/53

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