LP61L1024 查看數據表（PDF） - AMIC Technology

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LP61L1024

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

AMIC Technology 

Read Cycle 2 (1, 3, 4, 6)

CE1

DOUT

tCLZ15

tACE1

LP61L1024

tCHZ15

Read Cycle 3 (1, 4, 7, 8)

CE2

DOUT

tCLZ25

tACE2

tCHZ25

Read Cycle 4 (1)

Address

OE

CE1

CE2

DOUT

tRC

tAA

tOE

tOLZ5

tACE1

tCLZ25

tACE2

tCLZ25

tOH

tCHZ15

tOHZ5

tCHZ25

Notes:

1. WE is high for Read Cycle.

2. Device is continuously enabled CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

(August, 2004, Version 2.2)

6

AMIC Technology, Corp.

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