LSM330DLC 查看數據表（PDF） - STMicroelectronics
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LSM330DLC Datasheet PDF : 66 Pages
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Module specifications
LSM330DLC
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and TOP.
Table 6. SPI slave timing values
Symbol
Parameter
Value (1)
Min
Max
Unit
tc(SPC)
SPI clock cycle
100
ns
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
10
MHz
6
8
5
15
ns
tv(SO)
th(SO)
tdis(SO)
SDO valid output time
SDO output hold time
SDO output disable time
50
9
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not
tested in production.
Figure 3. SPI slave timing diagram(c)(d)
CS (3)
SPC (3)
tsu(CS)
SDI (3)
SDO (3)
tc(SPC)
tsu(SI)
th(SI)
MSB IN
tv(SO)
MSB OUT
th(SO)
(3)
th(CS)
(3)
LSB IN
(3)
tdis(SO)
LSB OUT
(3)
3. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.
c. The SDO output line features an internal pull-up.
d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
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Doc ID 022162 Rev 2
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