1840 查看數據表（PDF） - Linear Technology
零件编号
产品描述 (功能)
比赛名单
1840 Datasheet PDF : 12 Pages
| |||
LTC1840
U
OPERATIO
LTC1840 Device Addressing
Register Addresses and Contents
It is possible to configure the part to operate with any one
of nine separate addresses through the three state A0 and
A1 pins. Table 1 shows the correspondence of addresses
to the states of the pins:
Table 1. Device Addressing
LTC1840
Device Address
2-Wire Bus Slave Address Bits
(B7,B6,B5 = 111)
A0
A1
B4
B3
B2
B1
L
NC
0
0
0
0
NC
H
0
0
0
1
NC
NC
0
0
1
0
H
NC
0
0
1
1
L
L
0
1
0
0
H
H
0
1
0
1
NC
L
0
1
1
0
H
L
0
1
1
1
L
H
1
0
0
0
For the A0 and A1 lines, L refers to a grounded pin, H is a
pin shorted to VCC and NC is no connect. The pin voltage
will be set to approximately VCC/2 when not connected.
Bits B7, B6 and B5 of the address are hardwired to 111.
Table 2. LTC1840 Register Address and Contents
Fault conditions are cleared by the action of writing to the
fault register, but the data byte from the write command is
not actually loaded into the register.
A TACHA/B FLT (fault) bit will be high if the corresponding
TACHA/B FLTEN bit in the status register has been set high
and the corresponding TACHA/B counter has overflowed
its maximum count of 255. These faults are latched
internally and must be cleared by writing to the fault
register or by setting TACHA/B FLTEN low. The fault will be
reasserted if the counter is still in overflow after a write to
the fault register. The TACH FLT bits power-up in the low
state.
The blast and timer bits become high after blasting and
serial access time-out events, respectively.
A high GPIOX FLT bit reflects that the GPIOX pin has
caused a fault condition; to do so, the pin must be enabled
as fault producing in the GPIO setup register (GPIOX
FLTEN set high) and the logic state of the pin must change
after the enable. The fault is latched internally and must be
cleared through software by writing to the fault register or
by setting GPIOX FLTEN low; a change in the state of the
GPIOX pin from its state at the point of the fault register
being written will cause another fault to be signalled.
Register
Name
(R/W)
FAULT
STATUS
DACA
DACB
TACHA
TACHB
GPIO Data
GPIO Setup
Register
Address
R2 R1 R0
D7
D6
D5
000 TACHA FLT TACHB FLT
Blast
(0)
(0)
(0)
001 TACHA FLTEN TACHB FLTEN DIV1
(0)
(0)
(0)
010
MSB
Bit 6
Bit 5
(0)
(0)
(0)
011
MSB
Bit 6
Bit 5
(0)
(0)
(0)
100
Cnt A7
Cnt A6
Cnt A5
(1)
(1)
(1)
101
Cnt B7
Cnt B6
Cnt B5
(1)
(1)
(1)
110
GPIO4 Pin GPIO3 Pin GPIO2 Pin
(N/A)
(N/A)
(N/A)
111 GPIO4 BLNK GPIO3 BLNK GPIO2 BLNK
(0)
(0)
(0)
Data Byte
D4
D3
D2
D1
D0
Timer
(0)
GPI04 FLT
(0)
GPI03 FLT
(0)
GPI02 FLT
(0)
GPI01 FLT
(0)
DIV0
*See Note 2
(0)
(0/1)
(0)
(0)
(1)
Bit 4
Bit 3
Bit 2
Bit 1
LSB
(0)
(0)
(0)
(0)
(0)
Bit 4
Bit 3
Bit 2
Bit 1
LSB
(0)
(0)
(0)
(0)
(0)
Cnt A4
(1)
Cnt A3
(1)
Cnt A2
(1)
Cnt A1
(1)
Cnt A0
(1)
Cnt B4
(1)
Cnt B3
(1)
Cnt B2
(1)
Cnt B1
(1)
Cnt B0
(1)
GPIO1 Pin
(N/A)
GPIO4 Reg
(1)
GPIO3 Reg
(1)
GPIO2 Reg
(1)
GPIO1 Reg
(1)
GPIO1 BLNK GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN
(0)
(0)
(0)
(0)
(0)
Note 1: Number in ( )signifies default bit status upon power-up.
Note 2: State of bit depends on slave address used.
1840f
8
Share Link: 