LTC3732 查看數據表（PDF） - Linear Technology

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LTC3732

3-Phase, 5-Bit VID, 600kHz, Synchronous Buck Switching Regulator Controller

Linear Technology 

LTC3732

PI FU CTIO S

VID0 to VID4: Output Voltage Programming Input Pins. A

3µA internal pull-up current is provided on each input pin.

See Table 1 for details. Do not apply voltage to these pins

prior to the application of voltage on the VCC pin.

PLLIN: Synchronization Input to Phase Detector. This pin

is internally terminated to SGND with 50kΩ. The phase-

locked loop will force the rising top gate signal of control-

ler 1 to be synchronized with the rising edge of the PLLIN

signal.

PLLFLTR: The phase-locked loop’s lowpass filter is tied to

this pin. Alternatively, this pin can be driven with an AC or

DC voltage source to vary the frequency of the internal

oscillator. (Do not apply voltage directly to this pin prior to

the application of voltage on the VCC pin.)

FCB: Forced Continuous Control Input. The voltage ap-

plied to this pin sets the operating mode of the controller.

The forced continuous current mode is active when the

applied voltage is less than 0.6V. Burst Mode operation

will be active when the pin is allowed to float and a stage

shedding mode will be active if the pin is tied to the VCC pin.

(Do not apply voltage directly to this pin prior to the

application of voltage on the VCC pin.)

IN+, IN–: Inputs to a precision, unity-gain differential

amplifier with internal precision resistors. This provides

true remote sensing of both the positive and negative load

terminals for precise output voltage control.

DIFFOUT: Output of the Remote Output Voltage Sensing

Differential Amplifier.

EAIN: This is the input to the error amplifier which com-

pares the VID divided, feedback voltage to the internal

0.6V reference voltage.

PADDLE (UHF Package Only): This pin is connected to

the heat spreading metal pad at the center of the package

bottom and is tied to the IC’s substrate. It must be

connected to the SGND pin.

SGND: Signal Ground. This pin must be routed separately

under the IC to the PGND pin and then to the main ground

plane.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–,

SENSE3–: The Inputs to Each Differential Current Com-

parator. The ITH pin voltage and built-in offsets between

SENSE– and SENSE+ pins, in conjunction with RSENSE, set

the current trip threshold level.

8

RUN/SS: Combination of Soft-Start, Run Control Input

and Short-Circuit Detection Timer. A capacitor to ground

at this pin sets the ramp time to full current output as well

as the time delay prior to an output voltage short-circuit

shutdown. A minimum value of 0.01µF is recommended

on this pin.

ITH: Error Amplifier Output and Switching Regulator Com-

pensation Point. All three current comparator’s thresholds

increase with this control voltage.

PGND: Driver Power Ground. This pin connects directly to

the sources of the bottom N-channel external MOSFETs

and the (–) terminals of CIN.

BG1 to BG3: High Current Gate Drives for Bottom N-

Channel MOSFETs. Voltage swing at these pins is from

ground to VCC.

VCC: Main Supply Pin. Because this pin supplies both the

controller circuit power as well as the high power pulses

supplied to drive the external MOSFET gates, this pin

needs to be very carefully and closely decoupled to the IC’s

PGND pin.

DRVCC (UHF Package Only): This pin provides power to

the bottom MOSFET on-chip drivers. Tie this pin to the VCC

pin and carefully decouple this pin to the PGND pin with a

minimum of 5µF of ceramic capacitance immediately

adjacent to the IC package.

SW1 to SW3: Switch Node Connections to Inductors.

Voltage swing at these pins is from a Schottky diode

(external) voltage drop below ground to VIN (where VIN is

the external MOSFET supply rail).

TG1 to TG3: High Current Gate Drives for Top N-channel

MOSFETs. These are the outputs of floating drivers with a

voltage swing equal to the boost voltage source superim-

posed on the switch node voltage SW.

BOOST1 to BOOST3: Positive Supply Pins to the Topside

Floating Drivers. Bootstrapped capacitors, charged with

external Schottky diodes and a boost voltage source, are

connected between the BOOST and SW pins. Voltage

swing at the BOOST pins is from boost source voltage

(typically VCC) to this boost source voltage + VIN (where

VIN is the external MOSFET supply rail).

PGOOD: This open-drain output is pulled low when the

output voltage has been outside the PGOOD tolerance

window for the VPGDLY delay of approximately 100µs.

3732f

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