SM5838AS 查看數據表（PDF） - Nippon Precision Circuits

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SM5838AS

5120 × 8-bit Synchronous FIFO

Nippon Precision Circuits  

SM5838AS

1/2 Data Reduction

Input data rate reduction by half can be realized by

taking WE and RE simultaneously HIGH only once

every two clock cycles.

Noninterlace-to-interlace conversions line extraction

can be realized by switching WE LOW/HIGH in line

units and RE LOW/HIGH in word units.

1/2 data reduction

CLK

WE

RW

DIN

012345

nH

0123456789

RE

OE

RR

DOUT

nH-1H

0 2 4 6 8 10 12 14

5119

012

nH+1H

0123456789

5119

nH

5118 0 2 4 6 8 10 12 14

5119

5118

1/2 line extraction (noninterlace-to-interlace conversion)

CLK

WE

RW

DIN

012345

nH-1H

012345

RE

OE

RR

DOUT

012

1819

012

nH

012345

909

nH+1H

012345

909

nH-2H

909 0 1 2

nH+2H

012345

909

909

nH

909

NIPPON PRECISION CIRCUITS—11

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