SM5838AS 查看數據表（PDF） - Nippon Precision Circuits

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SM5838AS

5120 × 8-bit Synchronous FIFO

Nippon Precision Circuits  

SM5838AS

1/2n data reduction (n × n pixel reduction)

Screen resolution reduction, or 2 × 2 pixel reduction,

can be realized by combining both 1/2 data reduction

and 1/2 line extraction schemes. Furthermore, n × n

pixel reduction (for integer n) can be realized by

changing the WE and RE disable intervals and the

RW and RR reset timing.

Also, if the same data is repeatedly read out in place

of other data that has been discarded, the screen reso-

lution can be reduced without changing the data rate

to realize a mosaic filter function.

2 × 2 pixel reduction (1/4 reduction)

2 pixels

2 pixels

Valid Invalid

Invalid Invalid

CLK

WE

RW

DIN

012345

nH-1H

012345

RE

OE

RR

DOUT

0

2

909

nH

012345

909

nH-2H

nH+1H

012345

909

908

0

2

nH+2H

012345

909

909

nH

908

2 × 2 pixel reduction (mosaic)

2 pixels

Valid

2 pixels

CLK

WE

RW

DIN

RE

OE

RR

DOUT

909

012345

nH-1H

012345

nH

012345

909

nH+1H

012345

909

nH+2H

012345

909

nH-2H

nH-2H

0 2 4 6 908* 0 2 4

908 0

nH

2 4 6 908* 0

nH

24

*Output date 902 to 908 forms the preceding 1H data.

909

908

NIPPON PRECISION CIRCUITS—12

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