SM5838AS 查看數據表（PDF） - Nippon Precision Circuits

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SM5838AS

5120 × 8-bit Synchronous FIFO

Nippon Precision Circuits  

SM5838AS

Output Enable

When OE is HIGH, DOUT0 to DOUT7 become high

impedance. Note that because RE operation is inde-

pendent of OE operation, the read address pointer

can be incremented even when the outputs are high

impedance.

CLK

OE

n cycle

t CKW

t CKW

t OEH

t OES

tA

DOUT (n-1) ,,,,,,,,,,,,,,,,,,,,,,,,,,,, (n)

n+1 cycle

t OZ

n+2 cycle

n+3 cycle

t OEH

t OES

tA

Hi-Z

,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n+3)

t ZO

RR="H" ,RE="L"

TYPICAL APPLICATIONS

Note that at power-ON, the write address pointer and

read address pointer positions are undefined.

Accordingly, RW and RR reset cycles are required.

1H Delay Line

A 5120-word delay line can be realized by perform-

ing simultaneous write reset and read reset at power-

ON.

An n-word delay line (21 to 5210-word) can be real-

ized using any of the following methods.

1. Perform reset in sync with desired delay length.

2. Stagger RW and RR timing to desired delay

length.

3. Manipulate the write or read address pointer

using WE or RE to disable incrementing to

maintain sync with desired delay length.

1H (5120-word) delay line timing

1H

2H

CLK

0 cycle

1 cycle

2 cycle

5119

cycle

5120+0

cycle

5120+1

cycle

5120+2

cycle

5120+3

cycle

t t RS

RH

RW

RR

DIN

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

t

t DS

0

DH

,,,,,,,,,,,,,,,

1

,,,,,,,,,,,,,,, 2

,,,,,,,,,,,,,,, 5118 ,,,,,,,,,,,,,,, 5119 ,,,,,,,,,,,,,,, 0 ,,,,,,,,,,,,,,, 1 ,,,,,,,,,,,,,,, 2 ,,,,,,,,,,,,,,, 3

,,,,,,,,,,

5120 cycle

tA

t OH

DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 ,,,,,,,,,,,,,,, 1 ,,,,,,,,,,,,,,, 2 ,,,,,,,,,,,,,,, 3 ,,,,,,,,,,

WE="L" , RE="L" , OE="L"

NIPPON PRECISION CIRCUITS—8

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