M2V64S20BTP 查看數據表（PDF） - Mitsumi

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M2V64S20BTP

64M bit Synchronous DRAM

Mitsumi 

PC133 SDRAM (Rev.0.5)

Oct. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)

[ /CAS LATENCY ]

/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the

speed of CLK determines which CL should be used. First output data is available after CL

cycles from READ command.

/CAS Latency Timing(BL=4)

CLK

Command

Address

DQ

DQ

ACT

X

tRCD

READ

Y

CL=2

Q0 Q1 Q2 Q3

CL=3

Q0 Q1 Q2 Q3

CL=2

CL=3

[ BURST LENGTH ]

The burst length, BL, determines the number of consecutive writes or reads that will be

automatically performed after the initial write or read command. For BL=1,2,4,8, full page the

output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst

Terminate) command should be issued to stop the output of data.

Burst Length Timing( CL=2 )

tRCD

CLK

Command

ACT

READ

Address

X

DQ

DQ

DQ

DQ

DQ

Y

Q0

Q0 Q1

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

Qm Q0 Q1

BL=1

BL=2

BL=4

BL=8

BL=FP

M2V64S20B : m=1023

M2V64S30B : m=511

M2V64S40B : m=255

Full Page counter rolls over

and continues to count.

MITSUBISHI ELECTRIC

14

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