M2V64S20BTP 查看數據表（PDF） - Mitsumi

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M2V64S20BTP

64M bit Synchronous DRAM

Mitsumi 

PC133 SDRAM (Rev.0.5)

Oct. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)

CLK

Command

Address

DQ

Read

Y

Q0 Q1 Q2 Q3

Write

Y

D0 D1 D2 D3

CL= 3

BL= 4

/CAS Latency

Burst Length

Burst Type

Burst Length

Initial Address BL

Column Addressing

A2 A1 A0

Sequential

Interleaved

00 0

0 123 4 56 7 01 234 5 6 7

00 1

1 234 5 67 0 10 325 4 7 6

01 0

2 345 6 70 1 23 016 7 4 5

01 1

3 456 7 01 2 32 107 6 5 4

8

10 0

4 567 0 12 3 45 670 1 2 3

10 1

5 670 1 23 4 54 761 0 3 2

11 0

6 701 2 34 5 67 452 3 0 1

11 1

7 012 3 45 6 76 543 2 1 0

- 00

0 1 23

01 2 3

- 01

1 2 30

4

- 10

2 3 01

10 3 2

23 0 1

- 11

3 0 12

32 1 0

-- 0

01

2

-- 1

10

01

10

MITSUBISHI ELECTRIC

15

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