M2V64S20BTP 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M2V64S20BTP Datasheet PDF : 52 Pages
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SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1.Clock will be applied at power up along with power. Attempt to maintain CKE high,
DQM (x4,x8), DQMU/L (x16) high and NOP condition at the inputs along with power.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
CLK
programmed by setting the mode register (MRS). The mode
/CS
register stores these data until the next MRS command, which
/RAS
/CAS
may be issued when both banks are in idle state. After tRSC
/WE
from a MRS command, the SDRAM is ready for new command. BA0,1 A11-A0
V
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 WM 0 0 LTMODE BT
BL
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
/CAS LATENCY
R
R
2
3
R
R
R
R
WRITE
MODE
0 BURST
1 SINGLE BIT
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
BURST
TYPE
0 SEQUENTIAL
1
INTERLEAVE
R: Reserved for Future Use
FP: Full Page
MITSUBISHI ELECTRIC
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