M38C88EA-XXXFP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M38C88EA-XXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

PRELIMINARY NSocothimcaene:gpTeah.riasmisetnrioct laimfiintsalasrepescuibfijceacttioton.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by fifteen sources: six external, eight internal, and

one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an in-

terrupt request bit and an interrupt enable bit, and is controlled by the

interrupt disable flag. An interrupt occurs if the corresponding inter-

rupt request and enable bits are “1” and the interrupt disable flag is

“0”.

Interrupt enable bits can be set or cleared by software. Interrupt re-

quest bits can be cleared by software, but cannot be set by software.

The BRK instruction interrupt and reset cannot be disabled with any

flag or bit. The I flag disables all interrupts except the BRK instruction

interrupt and reset. If several interrupts requests occurs at the same

time the interrupt with highest priority is accepted first.

Interrupt Operation

By acceptance of an interrupt, the following operations are automati-

cally performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status reg-

ister are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

4. The interrupt jump destination address is read from the vector

table into the program counter.

sNotes on interrupts

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 3A16)

Timer X mode register (address 2716)

Timer Y mode register (address 2816)

•When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Related register: AD control regsiter (address 3116)

When not requiring for the interrupt occurrence synchronized with

these setting, take the following sequence.

➀Set the corresponding interrupt enable bit to “0” (disabled).

➁Set the interrupt edge select bit (active edge switch bit) or the inter-

rupt source select bit to “1”.

➂Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃Set the corresponding interrupt enable bit to “1” (enabled).

Table 6 Interrupt vector addresses and priority

Vector Addresses (Note 1)

Interrupt Source Priority

High

Low

Reset (Note 2)

1

FFFD16

FFFC16

INT0

2

FFFB16

FFFA16

INT1

3

FFF916

FFF816

Serial I/O

reception

Serial I/O

transmission

Timer X

Timer Y

Timer 2

Timer 3

CNTR0

4

FFF716

5

FFF516

6

FFF316

7

FFF116

8

FFEF16

9

FFED16

10

FFEB16

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

CNTR1

11

FFE916

FFE816

Timer 1

12

Key input (Key- 13

on wake-up)

A-D conversion 14

FFE716

FFE116

FFDF16

FFE616

FFE016

FFDE16

Interrupt Request

Generating Conditions

At reset

At detection of either rising or falling edge of

INT0 intput

At detection of either rising or falling edge of

INT1 input

At completion of serial I/O data reception

At completion of serial I/O transmission shift

or when transmission buffer is empty

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or falling edge of

CNTR0 input

At detection of either rising or falling edge of

CNTR1 input

At timer 1 underflow

At falling of port P2 (at input) input logical level

AND

At completion of A-D conversion

BRK instruction 15

FFDD16

FFDC16 At BRK instruction execution

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O is selected

Valid when serial I/O is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(falling valid)

Valid when A-D conversion interrupt

is selected

Non-maskable software interrupt

17

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