CY7C43686-15AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43686-15AC Datasheet PDF : 39 Pages
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CY7C43646
CY7C43666
CY7C43686
Pin Definitions (continued)
Signal Name Description I/O
Function
RT2
FIFO2
I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
Retransmit
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
SIZEB
Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A
LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZEB works with
BM and BE to select the bus size and endian arrangement for Port B. The level of
SIZEB must be static throughout device operation.
SIZEC
Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port C. A
LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZEC works with
BM and BE to select the bus size and endian arrangement for Port B. The level of
SIZEC must be static throughout device operation.
SPM
Serial
Programming
I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I A HIGH selects a write operation and a LOW selects a read operation on Port A for
a LOW-to-HIGH transition of CLKA. The A0−35 outputs are in the high-impedance state
when W/RA is HIGH.
WENC
Port C Write
Enable
I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data
on Port C.
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFC/IRC)
LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB)
LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost
Full flag (AFA, AFC) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after
power-up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determines the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Partial
Reset inputs can switch asynchronously to the clocks. A
Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the
Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) HIGH. A Partial Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to Port C or read
from Port B. This selection determines the order by which
bytes (or words) of data are transferred through these ports.
For the following illustrations, assume that a byte (or word) bus
size has been selected for Port B and Port C.
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the least significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port C to Port A, the byte (word) written to Port
C first will be transferred to Port A as the most significant byte
(word) of the long-word; the byte (word) written to Port C last
will be transferred to Port A as the least significant byte (word)
of the long- word.
A LOW on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
Document #: 38-06023 Rev. *C
Page 6 of 39
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