MCM56824AZP25R2 查看數據表（PDF） - Motorola => Freescale

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MCM56824AZP25R2

DSPRAM 8K x 24 Bit Fast Static RAM

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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by MCM56824A/D

DSPRAM™

8K x 24 Bit Fast Static RAM

MCM56824A

The MCM56824A is a 196,608 bit static random access memory organized as

8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple

chip enable inputs, output enable, and an externally controlled single address pin

multiplexer. These functions allow for direct connection to the Motorola

DSP56001 Digital Signal Processor and provide a very efficient means for imple-

mentation of a reduced parts count system requiring no additional interface logic.

The availability of multiple chip enable (E1 and E2) and output enable (G) in-

puts provides for greater system flexibility when multiple devices are used. With

either chip enable input unasserted, the device will enter standby mode, useful

in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the

highest order address input depending upon the state of the V/S control input.

This feature allows one physical static RAM component to efficiently store pro-

gram and vector or scalar operands by dynamically re–partitioning the RAM

array. Typical applications will logically map vector operands into upper memory

with scalar operands being stored in lower memory. By connecting

DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control

pin, such partitioning can occur with no additional components. This al-

lows efficient utilization of the RAM resource irrespective of operand

type. See application diagrams at the end of this document for addition-

DQ0

al information.

DQ1

Multiple power and ground pins have been utilized to minimize effects

DQ2

induced by output noise.

VSS

The MCM56824A is available in a 52 pin plastic leaded chip–carrier

DQ3

(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.

DQ4

DQ5

• Single 5 V ± 10% Power Supply

DQ6

• Fast Access and Cycle Times: 20/25/35 ns Max

• Fully Static Read and Write Operations

• Equal Address and Chip Enable Access Times

• Single Bit On–Chip Address Multiplexer

• Active High and Active Low Chip Enable Inputs

DQ7

DQ8

VSS

DQ9

DQ10

• Output Enable Controlled Three State Outputs

• High Board Density PLCC Package

• Low Power Standby Mode

• Fully TTL Compatible

FN PACKAGE

52–LEAD PLCC

CASE 778–02

9 x 10 GRID

86 BUMP PBGA

CASE 896A–01

PIN ASSIGNMENTS

PLCC

7 6 5 4 3 2 1 52 51 50 49 48 47

8

46

9

45

10

44

11

43

12

42

13

41

14

40

15

39

16

38

17

37

18

36

19

35

20 21

22 23

24

25

26

27 28

29

30 31

34

32 33

DQ23

DQ22

DQ21

VSS

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

VSS

DQ14

DQ13

VIEW OF PBGA PACKAGE BOTTOM

10 9 8 7 6 5 4 3 2 1

PIN NAMES

A0 – A11 . . . . . . . . . . . . . . . Address Inputs

A12, X/Y . . . . . . . . . . Multiplexed Address

V/S . . . . . . . . . Address Multiplexer Control

W . . . . . . . . . . . . . . . . . . . . . . . Write Enable

E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ23 . . . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . . . . +5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . No Connection

For proper operation of the device, all VSS

pins must be connected to ground.

DSPRAM is a trademark of Motorola, Inc.

REV 2

4/95

A

D13 VSS D16 D17 D18 D20 D21 D23

B

W D12 D14 D15

D19 VSS D22 A5 A4

C

E1 E2

A3 A2

D VSS VSS

E

VCC

A1 A0

VCC

F

G A6

G

A7 A8

V/S NC

A12 X/Y

H A9 D11 D9 D8

D4 VSS D1 A10 A11

J

D10 VSS D7 D6 D5 D3 D2 D0

Not to Scale

M© OMoTtoOroRla,OInLc.A19F95AST SRAM

MCM56824A

1

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