MCM56824AZP25R2 查看數據表（PDF） - Motorola => Freescale
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MCM56824AZP25R2 Datasheet PDF : 10 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM56824A–20 MCM56824A–25 MCM56824A–35
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Read Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Access Time
tAVQV
—
20
—
25
—
35
ns
MUX Control Valid to Output Valid
tVSVQV
—
20
—
25
—
35
ns
Chip Enable to Output Valid
tE1LQV
—
20
—
25
—
35
ns
4
tE2HQV
Output Enable to Output Valid
tGLQV
—
8
—
10
—
15
ns
Output Active from Chip Enable
tE1LQX
2
—
2
—
0
—
ns
4, 5
tE2HQX
Output Active from Output Enable
tGLQX
0
—
0
—
0
—
ns
5
Output Hold from Address Change
tAXQX
4
—
5
—
5
—
ns
Output Hold from MUX Control Change
tVSXQX
4
—
5
—
5
—
ns
Chip Enable to Output High–Z
tE1HQZ
0
10
0
15
0
15
ns
4, 5
tE2LQZ
Output Enable High to Output High–Z
tGHQZ
0
8
0
15
0
15
ns
5
NOTES:
1. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.
READ CYCLE
A (ADDRESS)
tAVAV
V/S (MUX CONTROL)
E1 (CHIP ENABLE)
G (OUTPUT ENABLE)
tAVQV
tVSVQV
tE1LQV
tGLQV
tAXQX
tVSXQX
tE1HQZ
Q (DATA OUT) HIGH–Z
tGLQX
tE1LQX
tGHQZ
DATA VALID
HIGH–Z
MCM56824A
4
MOTOROLA FAST SRAM
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