SAA2500H 查看數據表（PDF） - Philips Electronics

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SAA2500H

MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

MPEG Audio Source Decoder

Preliminary specification

SAA2500

During decoding, the SAA2500 de-multiplexes the MPEG

audio bitstream, and with knowledge of the ancillary

information, reconstructs and combines the sub-band

signals into a broadband audio output signal.

Basic functionality

From a functional point of view, several blocks can be

distinguished in the SAA2500. A clock generator section

derives the internally and externally required clock signals

from its clock inputs. The SAA2500 can switch between a

master and a slave input interface to receive the coded

input data. The input processor parses and de-multiplexes

the input data stream. The de-quantization and scaling

processor performs the transformation and scaling

operations on the sample representations in the input

bitstream to yield sub band domain samples.

The sub band samples are transferred via an external

detour to the synthesis sub band filter bank processor. The

detour can be used to process the decoded audio in the

sub band domain. The baseband audio samples,

reconstructed by the sub band filter bank, can be

processed before being output.

The decoding control block houses the L3 control

interface, and handles the response to external control

signals. The L3 control interface enables the application to

configure the SAA2500, to read its decoding status, to

read Ancillary Data, and so on.

Several pins are reserved for Boundary Scan Test and

Scan Test purposes.

SAA2500 clocks

The SAA2500 clock interfacing is designed for application

versatility. It consists of 10 signals (see Table 1).

From a functional point of view, the clock generator inside

the device can be represented as shown in Fig.3.

As described above, the SAA2500 incorporates a master

input interface on which it requests for coded input data

itself, as well as a slave input interface for an imposed

coded data input bitstream. The input interface is selected

with flags MSEL0 and MSEL1, controlled via the L3

microcontroller interface.

Depending on the selected input interface, only a limited

number of the three possible input clocks (MCLKIN, X22IN

and FSCLKIN) is actually required. The various clock

options are selected with the 3 external control signals

MCLK24, FSCLKM and FSCLK384. These control signals

must be stationary while the device reset signal RESET is

de-activated; changing any of these 3 signals without

simultaneously resetting the SAA2500 can result in

malfunctioning.

Table 1 Clock interfacing signals.

SIGNAL

MCLKIN

MCLKOUT

MCLK

MCLK24

X22IN

X22OUT

FSCLKIN

FSCLK

FSCLK384

FSCLKM

DIRECTION

input

output

output

input

input

output

input

output

input

input

FUNCTION

master clock oscillator input or signal input

master clock oscillator output

master clock; buffered signal

master clock frequency indication:

MCLK24 = 0; MCLKIN frequency is 12.288 MHz (256 × 48 kHz)

MCLK24 = 1; MCLKIN frequency is 24.576 MHz (512 × 48 kHz)

22.5792 MHz (512 × 44.1 kHz) clock oscillator input or signal input

22.5792 MHz (512 × 44.1 kHz) clock oscillator output

sample rate clock signal input

sample rate clock signal; buffered signal

sample rate clock signal frequency indication:

FSCLK384 = 0; FSCLKIN frequency is 256 times the sample rate

FSCLK384 = 1; FSCLKIN frequency is 384 times the sample rate

sample rate clock source selection when using the master input:

FSCLKM = 0; use MCLKIN or X22IN as source

FSCLKM = 1; use FSCLKIN as source

September 1994

6

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