SAA2500H 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

比赛名单

SAA2500H

MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

MPEG Audio Source Decoder

Preliminary specification

SAA2500

hahnadnbdobooko,kf,ufllupllapgaegweiwdtidhth

C2

10

X1

C1

C3

X2

C4

R1

9

R2

8

R4

7

R3

SAA2500

C1 =C2 = 33 pF;

R1 = R4 = 1 MΩ;

R2 = R3 = 1 kΩ;

X1 = 22.5792 MHz;

X2 = 24.5760 MHz or 12.2880 MHz

The specified component values only apply to crystals with a low equivalent series resistance of <40 Ω.

MGB492

Fig.4 Crystal oscillator components.

Clock frequencies when using the slave input

If the slave input is used (MSEL1 and MSEL0 = 10 or 11),

the SAA2500 clock sources are MCLKIN and FSCLKIN

and X22IN is not used. The I2S clocks SCK and WS are

generated by the SAA2500 from FSCLKIN. FSCLKIN may

be designated to have a frequency of 256 times (indicated

by FSCLK384 = 0) or 384 times (indicated by

FSCLK384 = 1) the sample frequency of the coded input

data. Master clock signal MCLKIN may be chosen to have

a frequency of 12.288 MHz (indicated by MCLK24 = 0) or

24.576 MHz (indicated by MCLK24 = 1). MCLKIN and

FSCLKIN do not have to be phase or frequency locked. If

the application is based on a sample frequency of 48 kHz

or 32 kHz, and a sample rate related clock of 12.288 MHz

(256 × 48 kHz; 384 × 32 kHz) is available, this can be

taken advantage of by using this signal for both MCLKIN

and FSCLKIN.

Clock frequencies when using the master input

If the master input is used (MSEL1 and MSEL0 = 00), one

out of two configurations is selected with signal FSCLKM

with respect to the clock sources:

1. If FSCLKM = 0, MCLKIN and X22IN are the clock

sources. FSCLKIN is not used in this configuration.

FSCLK384 must be set to 0 for reasons of internal

connections in the clock generator circuitry. MCLKIN

may have only frequency 24.576 MHz (so mandatory

accompanied by MCLK24 = 1), and X22IN must have

a frequency of 22.5792 MHz. MCLKIN and X22IN do

not have to be phase or frequency locked. The main

advantage of this configuration is that the SAA2500

determines automatically which sample rate is active

from the sampling rate setting of the input data

bitstream, and then selects either MCLKIN or X22IN

as the clock source for the I2S clocks SCK and WS.

This configuration is therefore particularly suited in

applications with more than one possible sample rate

setting.

2. If FSCLKM = 1, the configuration is comparable to the

configuration when using the slave input

(see Section “Clock frequencies when using the slave

input”). MCLKIN and FSCLKIN are used as the clock

sources, and X22IN is not required. MCLKIN may

again have a frequency of 12.288 MHz (indicated by

MCLK24 = 0) or 24.576 MHz (indicated by

MCLK24 = 1), and FSCLKIN may have a frequency of

256 times (indicated by FSCLK384 = 0) or 384 times

(indicated by FSCLK384 = 1) the sample frequency of

the input data. MCLKIN and FSCLKIN do not have to

be phase or frequency locked.

Target applications; applying the SAA2500 with 2

ISO/MPEG sources

In Table 2 the three target applications of the SAA2500 are

summarised. The slave input application is labelled S, and

the master input applications are labelled M0 and M1.

September 1994

8

Share Link: