MK50H28 查看數據表（PDF） - STMicroelectronics

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MK50H28

MULTI LOGICAL LINK FRAME RELAY CONTROLLER

STMicroelectronics 

MK50H28

Figure 3: MK50H28 Memory Management Structure

CSR2, CSR3

PTR TO INIT

INIT BLOCK

MODE

TIMER VALUES

PTR TO CT

PTR TO ALT

PTR TO TINT DR

PTR TO RINT DR

PTR TO STATUS

BUFFER

LMI ERROR

COUNTERS

ADDRESS

LOOKUP

TABLE

ACT. CHNL

(DLCI 0

to

DLCI 1024

or

DLCI 8192)

CONTEXT TABLE

(1 ENTRY/ACT. CHNL)

DESC RING PTRS

CONG STATISTICS

DLCI / ADDRESS

ACTIVE CHNL. 0

DESC RING PTRS

CONG STATISTIC S

DLCI / ADDRESS

ACTIVE CHNL. 1

DESC RING PTRS

CONG STATISTICS

DLCI / ADDRESS

ACTIVE CHNL. N

STATUS

BUFFER

XMIT RING0

DESC 0

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

DESC 1

DATA

BUFFERS

BUFF

0

BUFF

1

DESC M

BUFF

M

XMIT RING N

DESC 0

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

DESC 1

BUFF

0

BUFF

1

PRIORITY DLCI

BLOCK

TX INTERRUP T RING

DESC 0

TX CT Address

Current TX Desc

Service Bit

DESC 1

DESC 127

RX INTERRUPT RING

DESC 0

RX CT Address

Current RX Desc

Service Bit

DESC 1

DESC 127

DESC N

BUFF

N

RX RING 0

DESC 0

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

DESC 1

DATA

BUFFERS

BUFF

0

BUFF

1

DESC X

BUFF

X

RX RING N

DESC 0

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

DESC 1

DATA

BUFFERS

BUFF

0

BUFF

1

DESC Y

BUFF

Y

12/64

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