MP7651AS 查看數據表（PDF） - Exar Corporation

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MP7651AS

8-Channel, Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Data Port and Chip Select Decoder

Exar Corporation 

MP7651

THEORY OF OPERATION

MP7651 is equipped with a serial data 3-wire standard µ-

processor logic interface to reduce pin count, package size (28

pin), and board wire (space). This interface consists of LD which

controls the transfer of data to the selected DAC channel, SDI

(serial data/address input), CLK (shift register clock) and SDO

(serial data output). When the LD signal is high, CLK signal

loads the digital input bits (SDI) into the 16-bit shift register (8 bits

data D7 to D0, plus 4 bits address A3 to A0, and 4 bits of Chip

Select data CS0S to CS3S). If the CS0S to CS3S in the shift reg-

ister match the parallel chip-select address (CS0P to CS3P) for

the selected chip, then the LD signal going low loads the data

into the selected DAC of that chip. The LD signal going low also

disables the serial data input (SDI), output (SDO 3-stated) and

the CLK input. This design tremendously reduces digital noise,

and glitch transients into the DACs due to free running CLK and

SDI. Also, 3-stating the SDO output with LD signal would allow

read back of pre-stored digital data of the selected package us-

ing one SDO wire for all DAC ICs on the board. Note also that

the reset signal (RST) resets all analog outputs to 1/2 of VREF,

regardless of any digital inputs. Also note that the input VRi is

referenced to GND.

Function A3 A2 A1 A0

LD

CS0S CS1S CS2S CS3S CLK

Shift Data In

and Out

Stop Shifting

Data In and

Out

Load DACs

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

DAC 7

X XXX

1

X XXX

0

X X X X 0→1

Repeat

XX X X

X

0 0 0 0 No Operation

0 001

1→0

X

0 010

1→0

X

0 011

1→0

X

0 100

0 101

0 110

0 111

1 000

1→0

1→0

1→0

1→0

1→0

X

Matched with 4 parallel X

chip select data

X

CS0P to CS3P

X

X

No Operation

X

X

X

1 1 1 0 No Operation

X

1 1 1 1 No Operation

X

Reset all DACs X X X X

X

to VREF/2

XX X X

X

RST

SDI

1 Data Input

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

0

X

SDO

Data Output

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

X

Table 1. Digital Function Truth Table

Serial In/Serial Out

D7 D6 D5 D4 D3 D2 D1 D0 DAC Output Voltage

MSB

LSB

VOi

= AGND + (VRi –

AGND)

(

D

256

)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

AGND

(VRi

– AGND)

(

1

256

)

+ AGND

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

(VRi – AGND)

(

254

256

)

+

AGND

(VRi

– AGND)

(

255

256

)

+

AGND

Table 2. DAC Transfer Function

Analog Output vs. Digital Code

Rev. 2.00

7

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