MP8798 查看數據表（PDF） - Exar Corporation

零件编号

产品描述 (功能)

比赛名单

MP8798

CMOS Very Low Power, 1 MSPS 10-Bit Analog-to-Digital Converter with 4-Channel Mux

Exar Corporation 

MP8798

Figure 7. gives a visual definition of the INL error. The chart

shows a 3-bit converter transfer curve with greatly exaggerated

DNL errors to show the deviation of the real transfer curve from

the ideal one.

After a tester has measured all the transition voltages, the

computer draws a line parallel to the ideal transfer line. By defi-

nition the best fit line makes equal the positive and the negative

INL errors. For example, an INL error of –1 to +2 LSB’s relative

to the Ideal Line would be +1.5 LSB’s relative to the best fit line.

Output

Codes

7

Real Transfer Line

6

Best Fit Line

5

EFS

INL

4

3

Ideal Transfer Line

2

1

LSB

EZS

Analog Input (Volt)

Figure 7. INL Error Calculation

Clock and Conversion Timing

A system will clock the MP8798 continuously or it will give

clock pulses intermittently when a conversion is desired. The

timing of Figure 8a shows normal operation, while the timing of

Figure 8b keeps the MP8798 in balance and ready to sample the

analog input.

CLOCK

N

N+1

DATA

N

N+1

a. Continuous sampling

CLOCK

N

BALANCE

DATA

N

b. Single sampling

Figure 8. Relationship of Data to Clock

Analog Input

The MP8798 has very flexible input range characteristics.

The user may set VREF(+) and VREF(–) to two fixed voltages and

then vary the input DC and AC levels to match the VREF range.

Another method is to first design the analog input circuitry and

then adjust the reference voltages for the analog input range.

One advantage is that this approach may eliminate the need for

external gain and offset adjust circuitry which may be required

by fixed input range A/Ds.

The MP8798’s performance is optimized by using analog in-

put circuitry that is capable of driving the AIN input. Figure 9.

shows the equivalent circuit for AIN.

VDD

AIN

R Series

40Ω

4

R MUX

500Ω

15 pF

1 pF

4

10 pF

Control

Channel

Selection

40 Ω

300 Ω

φS

φS

87 pF

60 pF

φB

4 pF

87 pF

160 Ω

+

1/2 [ VREF(+)

+ VREF(–) ]

Figure 9. Analog Input Equivalent Circuit

Rev. 3.00

8

Share Link: