MP8830 查看數據表（PDF） - Exar Corporation

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MP8830

Triple 10-bit High Speed Analog-to-Digital Converter with Digitally Controlled References

Exar Corporation 

MP8830

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: AVDD = DVDD= 5 V, DGND = AGND = 0 V, VREF = AVDD  0.2

Temperature = 0 to 60°C1

A/D Converters

Parameter

Resolution

Differential Non-Linearity

Differential Non-Linearity

Integral Non-Linearity

Integral Non-Linearity

Zero Scale Error

Symbol

N

DNL

DNL

INL

INL

ZSE

Zero Scale Drift2

ZSD

DC Input Range

AIN

Data Rate

FS

Analog Input Voltage Change from

Sample to Sample2

Input Capacitance2

Gain DAC

Resolution

Differential Non-Linearity

Integral Non-Linearity

Gain DAC Full Scale

(VRT – VRB)

Gain DAC Zero Scale

(VRT – VRB)

Maximum Gain Change per Cycle2

DAIN

CIN

N

DNL

INL

GFS

GZS

MGC

Settling Time (MGC)2

ts-gd

Min

10

–1

–1

–15

VCLP

–5mV

1.25

0

Typ

0.75

0.5

2

1.5

50

Max Units

Bits

2 LSB

2 LSB

2.75 LSB

2 LSB

9 mV

µV/°C

2.92 V + V

VCLP

–5 mV

MSPS

FS V

45 pF

Test Conditions/Comments

Gain DAC = 000 (hex), offset DAC = 00 (hex).

Monotonicity guaranteed.

Gain DAC = 1FF (hex), offset DAC = 00 (hex).

Monotonicity guaranteed.

Gain DAC = 000 (hex), offset DAC = 00 (hex),

Best fit straight line.

Gain DAC = 1FF (hex), offset DAC = 00 (hex),

Best fit straight line.

Measured with offset and gain DACs set to

000. Offset is defined as the difference be-

tween the clamp voltage and the analog input

voltage which results in the transition of the

ADC code from 004 to 005.

Measured as the change in the ZSE over tem-

perature. This error does not include the error

introduced by the external VREF amplifier or

external VREF resistor divider.

The digitizing range is set with the Gain DAC

and offset DAC. Please note AIN (min) is

VCLP – 4 LSB = VRB and AIN (max) is GFS

(max) + ZSR (max) + VCLP – 4 LSB.

The conversion rate is determined by the tim-

ing diagram and timing specifications. Set by

the CVL period.

Assuming AIN voltage remains within the spe-

cified digitizing range based on the offset and

gain DAC codes.

Measured with AIN DC = 2.5 V and AENL =

low.

9

Bits

–1

+2.25 LSB

+2 LSB

2.6

2.68

2.76 V

Gain DAC = 1FF

VRT is the top of the ADC reference ladder.

Refer to block diagram.

1.22

1.26

1.3 V

Gain DAC = 000

VRB is the bottom of the ADC reference lad-

der. Refer to block diagram.

50 % FSR

After the specified maximum change in gain

DAC setting, the ADC should output the same

code 1 LSB for all of the following conver-

sions assuming the analog input remains

fixed, i.e. DC.

200

ns

Rev. 1.00

4

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