MP8830 查看數據表（PDF） - Exar Corporation
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MP8830 Datasheet PDF : 20 Pages
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MP8830
Parameter
Offset DAC
Resolution
Differential Non-Linearity
Integral Non-Linearity
VRB Range
Symbol
Min
Typ
N
DNL
INL
ZSR
6
–0.5
152
158
Maximum Offset Change per Cycle2 MOC
Full Scale Settling Time2
ts-od
200
Black Level Clamp Switch
On Resistance
Input Leakage
Clamp Switching Charge Injection2
Voltage at Clamp Pin
RON
ILCLP
QCLP
VCLP
100
170
180
Reference Voltage Requirements (See Theory of Operation)
Reference Voltage
VREF
0.93
1
Calibration Voltage
Sense Pins Input Resistance
(ASENS, BSENS, CSENS)
0.5
VCAL
AGND
RINS
560
Power Supplies (Note: All GND pins are substrate)
Analog Positive Supply
Digital Positive Supply
Analog Negative Supply
AVDD
DVDD
AGND
4.75
AVDD
0
Digital Negative Supply
DGND
0
Power Supply Rejection
PSRR
Supply Current
IDD
Digital Characteristics
Digital Input High Voltage for Control VIH
3.5
Pins
Digital Input Low Voltage for Control VIL
Pins
Digital Input High Voltage for DAC
VIH
2.4
Input Pins
Digital Input Low Voltage for DAC
VIL
Input Pins
VOL
VOL
VOH
VOH
4.5
Digital Input Leakage Current
IIN
–10
Rev. 1.00
5
AVDD
0
0
100
5
Max Units Test Conditions/Comments
Bits
0.5 LSB
1 LSB
164 mV
This is measured as the voltage difference at
the clamp pin of the selected channel when
the offset DAC changed from 000 (hex) to 3F
(hex) with the gain DAC at 1FF (hex). Refer
to VRT and VRB EQNs in the theory of opera-
tion section.
100 % FSR
After the specified maximum change in offset
DAC setting, the ADC should output the same
code 1 LSB for all of the following conver-
sions assuming the analog input remains
fixed, i.e. DC.
ns
For a 00 (hex) to 3F (hex) change of offset
DAC code.
150 Ω
25 nA
50 pC
190 mV
Effective RIN at clamp pin.
Offset DAC at 00 (hex) (worst case condition).
Offset DAC at 00 (hex) (worst case condition).
Offset by 4 LSB from bottom tap of ADC lad-
der. Gain = 000 (H). Offset DAC = 00.
1.07 V
1.15 V
AVDD V
Ω
All linearity specifications assume the refer-
ence voltage = AVDD X ( 0.2 ).
Functional.
RINS is measured from the sense pin to
AGND2, BGND2, CGND2 with the power
turned off and test voltage less than 250 mV.
5.25 V
AVDD V
0V
0V
–60 dB
130 mA
Bypass power supply pins.
Bypass power supply pins.
f=1 KHz.
During specified operation.
V
1.5 V
V
0.4 V
0.5 V
10 µA
All digital input pins other than DAC data
inputs.
All digital input pins other than DAC data
inputs.
DAC data inputs, CD0-CD14
DAC data inputs, CD0-CD14
@ IOL = 4 mA
@ IOH = 4 mA
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