MPC9893 查看數據表（PDF） - Motorola => Freescale
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MPC9893 Datasheet PDF : 16 Pages
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Freescale Semiconductor, Inc.
MPC9893
Table 1: PIN CONFIGURATION
Pin
I/O
CLK0, CLK1
Input
FB
Input
REF_SEL
Input
MAN/A
Input
ALARM_RST
Input
PLL_EN
FSEL[0:3]
Input
Input
OE/MR
QA[0:5]
Input
Output
QB[0:5]
QFB
Output
Output
ALARM0
Output
ALARM1
Output
CLK_IND
GND
VCC_PLL
Output
Supply
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
Supply
VCC
Function
PLL reference clock inputs
PLL feedback signal input, connect directly to QFB output
Selects the primary reference clock
Selects automatic switch mode or manual reference clock selection
Reset of alarm flags and selected reference clock
Select PLL or static test mode
Clock frequency selection and configuration of clock divider modes
Output enable/disable and device reset
Bank A clock outputs
Bank B clock outputs
Clock feedback output. QFB must be connected to FB for correct operation
Indicates clock failure on CLK0
Indicates clock failure on CLK1
Indicates currently selected input reference clock
Negative power supply
Positive power supply for the PLL (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin VCC_PLL. Please see
the application section for details.
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
Inputs
PLL_EN
0
PLL enabled. The input to output frequency
PLL bypassed and IDCS disabled. The VCO output is
relationship is that according to Table 3 if the PLL is replaced by the reference clock signal fref. The
frequency locked.
MPC9893 is in manual mode.
MAN/A
1
Manual clock switch mode. IDCS disabled. Clock
Automatic clock switch mode. IDCS enabled. Clock
failure detection and output flags ALARM0, ALARM1, failure detection and output flags ALARM0, ALARM1,
CLK_IND are enabled.
CLK_IND are enabled. IDCS overrides REF_SEL on
a clock failure. IDCS operation requires PLL_EN = 0.
ALARM_RST
REF_SEL
FSEL[0:3]
1
0
0000
ALARM0, ALARM1 and CLK_IND flags are reset:
ALARM0=H, ALARM1=H and CLK_IND=REF_SEL.
ALARM_RST is an one-shot function.
ALARM0, ALARM1 and CLK_IND active
Selects CLK0 as the primary clock source
Selects CLK1 as the secondary clock source
See Following Table
OE/MR
0
Outputs enabled (active)
Outputs disabled (high impedance tristate), reset of
data generators and output dividers. The MPC9893
requires reset at power-up and after any loss of PLL
lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than two reference clock
cycles (CLK0,1). MR/OE does not tristate the QFB
output.
Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked)
ALARM0
CLK0 failure
ALARM1
CLK_IND
CLK1 failure
CLK0 is the reference clock
CLK1 is the reference clock
TIMING SOLUTIONS
For More Informa3tion On This Product,
Go to: www.freescale.com
MOTOROLA
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