MPC9893 查看數據表（PDF） - Motorola => Freescale
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MPC9893 Datasheet PDF : 16 Pages
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MPC9893
Freescale Semiconductor, Inc.
Table 8: AC CHARACTERISTICS (VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = --40° to 85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
FSEL= 000x
15.0
FSEL= 001x
30.0
FSEL= 010x
40.0
FSEL= 011x
30.0
FSEL= 100x
60.0
FSEL= 101x
15.0
FSEL= 110x
30.0
FSEL= 111x
60.0
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fMAX
Maximum Output Frequency
FSEL= 000x
60.0
FSEL= 001x
60.0
FSEL= 010x
60.0
FSEL= 011x
30.0
FSEL= 100x
60.0
FSEL= 101x
7.5
FSEL= 110x
15.0
FSEL= 111x
30.0
200.0
200.0
200.0
100.0
200.0
25.0
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
frefDC
tr, tf
Reference Input Duty Cycle
CLK0, 1 Input Rise/Fall Time
40
60
%
1.0
ns
0.8 to 2.0V
t(∅)
∆t
tsk(O)
Propagation Delay (static phase offset, CLKx to FB)
VCC=3.3V±5% and FSEL[0:2]=111
VCC=3.3V±5%
VCC=2.5V±5% and FSEL[0:2]=111
VCC=2.5V±5%
Rate of period change (phase slew rate)
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
Output-to-output Skewb
(within bank)
(bank-to-bank)
(any output to QFB)
--60
-200
-125
-400
+50
+100
+25
+100
150
150
300
50
100
125
ps
ps
ps
ps
ps/cycle
PLL locked
Failover
switch
ps
ps
ps
DCO
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
Output duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitterc
45
0.1
FSEL3=0
FSEL3=1
tJIT(PER)
Period Jitterc
FSEL3=0
FSEL3=1
tJIT(∅)
BW
I/O Phase Jitterd
FB=4: FSEL[0:2]=100 or 111
FB=6: FSEL[0:2]=010
FB=8: FSEL[0:2]=001, 011, or 110
FB=16: FSEL[0:2]=000 or 101
RMS (1 σ)
RMS (1 σ)
RMS (1 σ)
RMS (1 σ)
PLL closed loop bandwidthe
FSEL=111x
50
0.8-4.0
55
%
1.0
ns
0.55 to 2.4V
10
ns
10
ns
225
ps
See
425
ps
applications
section
150
ps
See
250
ps
applications
section
See
40
ps
applications
50
ps
section
55
ps
70
ps
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. See application section for part-to-part skew calculation.
c. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section on page 9.
d. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See application section on page 8 and 9 for more
information and for the calculation for other confidence factors than 1σ.
e. -3dB point of PLL transfer characteristics.
MOTOROLA
For More Informa6tion On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
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