MSM7580 查看數據表（PDF） - Oki Electric Industry
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MSM7580 Datasheet PDF : 18 Pages
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¡ Semiconductor
MSM7580
NOTES ON USAGE
(1) Through Mode (CODER Side)
t0
t1
BCLK 1 2 3 4 5 6 7 8
PCM side SYNC (SYNCP)
PCM Input (SIP)
PCMDATA1
Internal Latch Timing
(A)
ADPCM side SYNC (SYNCA)
Through-Data Output (SOA)
ADPCMDATA0
PCMDATA2
ADPCMDATA1
PCMDATA3
ADPCMDATA2
(B)
ADPCM side SYNC (SYNCA)
Through-Data Output (SOA)
ADPCMDATA0
ADPCMDATA1
*t1 is the falling edge of the 8th BCLK counted from t0.
(A) When SYNCA rises after t1, PCMDATA1 is output to ADPCMDATA1.
(B) When SYNCA rises before t1, PCMDATA1 is output to ADPCMDATA1.
If SYNCA rises near the t1 and jitter occurs, data slip may occur. Therefore SYNCA should not rise in the range of ±500ns from t1.
Data slip means that data is deleted or the same data is output twice.
(2) Through Mode (DECODER Side)
t0
t1
BCLK 1 2 3 4 5 6 7 8
ADPCM side SYNC (SYNCA)
ADPCM Input (SIA)
ADPCMDATA1
Internal Latch Timing
(A)
PCM side SYNC (SYNCP)
Through-Data Output (SOP)
PCMDATA0
ADPCMDATA2
PCMDATA1
ADPCMDATA3
PCMDATA2
(B)
PCM side SYNC (SYNCP)
Through-Data Output (SOP)
PCMDATA0
PCMDATA1
*t1 is the falling edge of the 8th BCLK counted from t0.
(A) When SYNCA rises after t1, ADPCMDATA1 is output to PCMDATA1.
(B) When SYNCA rises before t1, ADPCMDATA1 is output to PCMDATA1.
If SYNCP rises near the t1 and jitter occurs, data slip may occur. Therefore SYNCA should not rise in the range of ±500ns from t1.
Data slip means that data is deleted or the same data is output twice.
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