MSM7716 查看數據表（PDF） - Oki Electric Industry

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MSM7716

Single Rail Linear CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7716

VFO

Receive filter output.

The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when

the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more.

This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments.

During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a

high impedance state.

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver.

The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted

with the pins PWI, AOUT–, and VFO described above.

The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1.

The output signal amplitudes are a maximum of 2.0 VPP.

These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a

minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT–).

The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be

mute controlled externally. These outputs are operational during power saving and output the

SG voltage (VDD/2) in the high impedance state.

AUXO

Auxiliary receive filter output.

The output signal is inverted with respect to the VFO output with a gain of 1. The output signal

swings above and below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kW with

respect to the SG voltage.

The output can be mute controlled externally.

During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high

impedance state.

BCLK

Shift clock signal input for PCMIN and PCMOUT.

The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit

and receive circuits to the power-saving state.

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