MSM7716 查看數據表（PDF） - Oki Electric Industry
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MSM7716 Datasheet PDF : 22 Pages
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¡ Semiconductor
MSM7716
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
VAIN
VDIN
TSTG
Condition
AG = DG = 0 V
AG = DG = 0 V
AG = DG = 0 V
—
Rating
Unit
–0.3 to +7.0
V
–0.3 to VDD + 0.3
V
–0.3 to VDD + 0.3
V
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
Condition
VDD
—
Ta
—
VAIN Gain = 1
High Level Input Voltage
Low Level Input Voltage
VIH SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
VIL
Min.
2.7
–30
—
0.45 ¥
VDD
0
Typ.
3.0
+25
—
—
—
Max.
3.6
+85
1.4
Unit
V
°C
VPP
VDD
V
0.16 ¥
V
VDD
Clock Frequency
FC BCLK
14 ¥ Fs — 128 ¥ Fs kHz
Sync Pulse Frequency
FS SYNC
4.0
8.0
Clock Duty Ratio
DC BCLK
40
50
Digital Input Rise Time
tIr SYNC, BCLK, PCMIN, PDN,
—
—
Digital Input Fall Time
tIf DEN, DCLK, CDIN
—
—
Sync Pulse Setting Time
tXS, tRS BCLKÆSYNC, See Fig.1
tSX, tSR SYNCÆBCLK, See Fig.1
100
—
100
—
High Level Sync Pulse Width *1 tWSH SYNC, See Fig.1
1 BCLK —
Low Level Sync Pulse Width *1 tWSL SYNC, See Fig.1
1 BCLK —
PCMIN Setup Time
tDS Refer to Fig.1
100
—
PCMIN Hold Time
tDH Refer to Fig.1
100
—
Digital Output Load
RDL Pull-up resistor
CDL
—
0.5
—
—
—
DCLK Pulse Width
tWCL DCLK Low width, See Fig.2
50
—
tWCH DCLK High width, See Fig.2
50
—
DEN Setting Time 1
tCDL DCLKÆDEN, See Fig.2
tDCL DENÆDCLK, See Fig.2
50
—
50
—
DEN Setting Time 2
tCDH DCLKÆDEN, See Fig.2
tDCH DENÆDCLK, See Fig.2
50
—
50
—
CDIN Setup Time
tCDS See Fig.2
50
—
CDIN Hold Time
tCDH See Fig.2
50
—
Transmit gain stage, Gain = 0 dB –100
—
Analog Input Allowable DC Offset Voff Transmit gain stage, Gain = 20 dB –10
—
Allowable Jitter Width
— SYNC, BCLK
—
—
16 kHz
60
%
50
ns
50
ns
—
ns
—
ns
—
—
—
—
—
ns
—
ns
—
kW
100 pF
—
ns
—
—
ns
—
—
ns
—
—
ns
—
+100 mV
+10 mV
1000 ns
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is
2048 kHz.
9/22
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