MT8920 查看數據表（PDF） - Mitel Networks
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MT8920 Datasheet PDF : 24 Pages
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MT8920B CMOS
C4i 1
F0i 2
IACK, MS1 3
STi0 4
CS 5
DS, OE 6
R/W, WE 7
A0 8
A1 9
A2 10
A3 11
A4 12
A5, STCH 13
VSS 14
28 VDD
27 MMS
26 DTACK, BUSY, DCS
25 IRQ, 24/32
24 STo1
23 STo0
22 D7
21 D6
20 D5
19 D4
18 D3
•
CS 5
25 IRQ, 24/32
DS, OE 6
24 STo1
R/W, WE 7
A0 8
23 STo0
22 D7
A1 9
21 D6
A2 10
20 D5
A3 11
19 D4
17 D2
16 D1
15 D0
28 PIN PDIP/CERDIP/SOIC
Pin Description
28 PIN J-LEAD
Figure 2 - Pin Connections
Pin #
1
2
3
4
5
6
7
8-12
Name
Description‡
C4i 4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial
bus.
F0i Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS
stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of
a frame.
IACK
MS1
Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is
an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will
output a user-programmed vector number on D0 - D7 indicating the source of the interrupt.
Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low
applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)
STi0 ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream.
CS Chip Select. This active low input is used to select the STPA for a parallel access .
DS Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data
bus during a write operation or that the STPA must output valid data on the data bus during a
read operation.
OE Output Enable (Mode 2). This active low input enables the data bus driver outputs.
OE Output Enable (Mode 3). This active low output indicates that the selected device is to be
read and that the data bus is available for data transfer.
R/W Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write
(R/W= 0) cycle.
WE Write Enable (Mode 3). This active low output indicates the data on the data bus is to be
written into the selected location of an external device.
A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port
memories of the STPA.
A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the
position in internal RAM where the information will be fetched from or stored in. Addresses
generated in this mode are used to access external devices for direct memory transfer.
3-4
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