MT9075B 查看數據表（PDF） - Zarlink Semiconductor Inc

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MT9075B

E1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9075B

Data Sheet

Pin Description (continued)

Pin #

PLCC MQFP

Name

Description

42 23

RxMF

Receive Multiframe Boundary (Output). An output pulse delimiting the received

multiframe boundary. The next frame output on the data stream (DSTo) is basic frame

zero on the PCM 30 link. This receive multiframe signal can be related to either the

receive CRC multiframe (page 01H, address 10H, bit 6, MFSEL=1) or the receive

signalling multiframe (MFSEL=0).

43 24 BS/LS System Bus Synchronous/Line Synchronous Selection (Input). If high, C4b and F0b

will be inputs; if low, C4b and F0b will be outputs.

44 32

E2o 2.048 MHz Extracted Clock (Output). The clock extracted from the received signal

and used internally to clock in data received on RTIP and RRING.

45 33

C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and

transmit serial PCM data of the MT9075B. In the free-run (BL/FR=0) or line synchronous

mode (BL/FR=1 and BS/LS=0) this signal is an output, while in the system bus

synchronous mode (BS/LS=1) this signal is an input clock.

46 34

F0b Frame Pulse (Input/Output). This is the ST-BUS or GCI frame synchronization

signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the

PCM30 link. In the free-run (BL/FR=0) or loop synchronous mode (BL/FR=1 and

BS/LS=0) this signal is an output, while in the Bus Synchronous mode (BL/FR=1 and

BS/LS=0) this signal is an input. The GCI/ST-BUS selection is made under software

control. Page 02H, address 13H, bit 0, GCI/ST=1 selects GCI frame pulse; GCI/ST=0

selects ST-BUS.

47 35 RxFP/Rx6 Receive Frame Pulse/Receive CCS Clock (Output). An 8 kHz pulse signal, which is

4KCK low for one extracted clock period. This signal is synchronized to the receive PCM 30

basic frame boundary.

When 64KCCS (page 01H, address 1AH, bit 0) is set to 1, this pin outputs a 64 kHz clock

derived by dividing down the extracted 2.048 MHz clock. This clock is used to clock CCS

data out of pin CSTo in the CCS mode.

48 36

IC Internal Connection. Must be left open for normal operation.

49 37

VSS Negative Power Supply (Input). Digital ground.

50 38

VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).

51 39 VDDATx Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter (+5V ±

5%).

52 40 TTIP Transmit TIP and RING (Outputs). Differential outputs for the transmit line signal - must

53 41 TRING be transformer coupled (See Figure 4).

54 42 GNDATx Transmit Analog Ground (Input). Analog ground for the LIU transmitter.

55 43

Tdi IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high.

56 44 Tdo IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected.

57 45 Tms IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled high.

58 46 Tclk IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high.

59 47 Trst IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low.

6

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