MT9075B 查看數據表（PDF） - Zarlink Semiconductor Inc

零件编号

产品描述 (功能)

比赛名单

MT9075B

E1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9075B

Data Sheet

bit, LLOS (bit 4 in page 3, register 18H) is provided to indicate the presence of a loss signal condition. The

occurrence of a loss signal condition is defined as per I.431, i.e., when the incoming signal amplitude is more than

20 dB below the nominal amplitude for a time duration of at least 1 ms.

The receive LIU circuit requires a terminating resistor of either 120 Ω or 75 Ω across the device side of the

receive1:1 transformer as shown in Figure 4. The return loss of the receiver, complying with G.703, is greater

than:

• 12 dB from 51 kHz to 102 kHz;

• 18 dB from 102 kHz to 2048 kHz;

• 14 dB from 2048 kHz to 3072 kHz.

The jitter tolerance of the MT9075B clock extractor circuit exceeds the requirements of G.823 (Figure 3).

Transmitter

The MT9075B differential line driver is designed to drive a 1:2 step-up transformer (see Figure 4). A 0.68 uF

capacitor is required between the TTIP and the transmit transformer. Resistors RT (as shown in Figure 4) are for

termination for transmit return loss. The values of RT may be optimized for 120 Ω lines, 75 Ω lines or set at an

intermediary value to serve both applications. Program the Transmit Pulse Control Word (address 1FH page 1) to

adjust the pulse amplitude accordingly. Alternatively, the pulse level and shape may be discretely programmed by

writing to the Customer Pulse Level registers (addresses 1CH to 1FH, page 2) and setting the Custom Transmit

Pulse bit high (bit 3 of the Transmit Pulse Control Word).

Peak to Peak

Jitter Amplitude

(log scale)

18UI

MT9075B

Tolerance

1.5UI

0.2UI

1.667Hz 20Hz

Jitter Frequency

(log scale)

2.4kHz 18kHz 100kHz

Figure 3 - Typical Jitter Tolerance

9

Zarlink Semiconductor Inc.

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