M5M4V64S20ATP-12 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M4V64S20ATP-12 Datasheet PDF : 51 Pages
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SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the
speed of CLK determines which CL should be used. First output data is available after CL cycles
from READ command.
/CAS Latency Timing(BL=4)
CLK
Command
Address
DQ
DQ
ACT
tRCD
X
READ
Y
CL=2
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be
automatically
performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated
(Hi-Z)
after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be
used to stop the output of data.
Burst Length Timing( CL=2 )
tRCD
CLK
Command
ACT
READ
Address
X
DQ
DQ
DQ
DQ
DQ
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Qm Q0 Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
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